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| document number: 326773-001 intel ? xeon ? processor e3-1200 v2 product family datasheet ? volume 2 of 2 may 2012
2 datasheet, volume 2 information in this document is prov ided in connection with intel products . no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and condit ions of sale for such products, in tel assumes no liability whatsoever and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. a "mission critical application" is any application in which fail ure of the intel product could result, directly or indirectly, in personal injury or death. should you purchase or use intel's pr oducts for any such mission critical application, you shall indemnify and hold intel and its subsidiaries, subcontractors and affiliates, and the directors, officers, and employees of each, harmless against all claims costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such mission critical applic ation, whether or not intel or its subcontractor was negligent in the design, manufacture, or warning of the intel product or any of its parts. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions mark ed "reserved" or "undefined". intel reserves these for future definition and shall have no responsibility wh atsoever for conflicts or incompatibilitie s arising from future changes to them. the information here is subject to change without notice. do not finalize a design with this information. the products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obta in the latest specifications an d before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm. intel ? active management technology requires activation and a system with a corporate network connection, an intel ? amt- enabled chipset, network hardware and software. for notebooks, intel amt may be unavailable or limited over a host os-based vpn, when connecting wirelessly, on battery power, sleeping, hibernating or powered off. results dependent upon hardware, setup & configuration. for more information, visit http://www.intel.com/technology/platform-technology/intel-amt no computer system can provide absolute security under all conditions. intel ? trusted execution technology (intel ? txt) requires a computer system with intel ? virtualization technology, an intel txt-enabled processor, chipset, bios, authenticated code modules and an intel txt-compatib le measured launched environment (mle). intel txt also requires the system to contain a tpm v1.s. for more information, visit http://www.intel.com/technology/security intel ? virtualization technology requires a computer system with an enabled intel ? processor, bios, virtual machine monitor (vmm). functionality, performance or othe r benefits will vary dependin g on hardware and software configurations. software applications may not be compatible with all operating systems. consult your pc manufacturer. for more information, visit http://www.intel.com/go/virtualization warning: altering clock frequency and/or voltage may (i) reduce sy stem stability and useful life of the system and processor; ( ii) cause the processor and other system components to fail; (iii) ca use reductions in system performance; (iv) cause additional he at or other damage; and (v) affect system data integrity. intel has not tested, and does not warranty, the operation of the proces sor beyond its specifications. requires a system with a 64-bit enabled proc essor, chipset, bios and software. performance will va ry depending on the specific hardware and software you use. consult your pc manufact urer for more information. for more information, visit http://www.intel.com/info/em64t enabling execute disable bit functionality re quires a pc with a processor with execut e disable bit capability and a supporting operating system. check with your pc manufacturer on whet her your system delivers execute disable bit functionality. enhanced intel speedstep ? technology: see the processor spec finder at http://ark.intel.com or contact your intel representative for more information. all products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. all dates specified are target dates, are prov ided for planning purposes only and are subject to change. intel, intel xeon, and the intel logo are trademarks of intel corp oration in the u.s. and other countries. *other names and brands may be cl aimed as the property of others. copyright ? 2012, intel corporation. all rights reserved. datasheet, volume 2 3 contents 1introduction ............................................................................................................ 13 2 processor configuration registers ........................................................................... 15 2.1 register terminology ......................................................................................... 15 2.2 pci devices and functions........................... ....................................................... 16 2.3 system address map ......................................................................................... 17 2.3.1 legacy address range ......................................................................... 19 2.3.1.1 dos range (0h?9_ffffh) .. ............ ........... ............ ......... ............ 20 2.3.1.2 legacy video area (a_0000h?b_ffffh ) .......... .......... ........... ........ 20 2.3.1.3 pam (c_0000h?f_ffffh) ... ............ ........... ............ ......... ............ 21 2.3.2 main memory address range (1 mb ? tolud)......................................... 22 2.3.2.1 isa hole (15 mb ? 16 mb) ......................................................... 22 2.3.2.2 tseg ...................................................................................... 23 2.3.2.3 protected memory range (pmr) ? (programmable) ....................... 23 2.3.2.4 dram protected range (dpr) ..................................................... 24 2.3.2.5 pre-allocated memory................................................................ 24 2.3.2.6 graphics stolen spaces ............................................................. 24 2.3.2.7 intel? management engine (intel? me) uma ............................... 25 2.3.3 pci memory address range (tolud ? 4 gb)........................................... 25 2.3.3.1 apic configuration space (fec0_0000h ? fecf_ffffh) ................. 26 2.3.3.2 hseg (feda_0000h ? fe db_ffffh) ........... ............ ......... ............ 27 2.3.3.3 msi interrupt memory space (fee0_0000 ? feef_ffff) .......... ...... 27 2.3.3.4 high bios area ........................................................................ 27 2.3.4 main memory address space (4 gb to touud)........................................ 27 2.3.4.1 memory re-claim background .................................................... 28 2.3.4.2 indirect accesses to mchbar registers........................................ 29 2.3.4.3 memory remapping .................................................................. 29 2.3.4.4 hardware remap algorithm........................................................ 29 2.3.4.5 programming model .................................................................. 30 2.3.5 pci express* configuration address space ............................................. 35 2.3.6 pci express* graphics attach (peg) ...................................................... 35 2.3.7 graphics memory address ranges ......................................................... 36 2.3.7.1 iobar mapped access to device 2 mmio space ............................ 36 2.3.7.2 trusted graphics ranges ........................................................... 36 2.3.8 system management mode (smm) ......................................................... 37 2.3.9 smm and vga access through gtt tlb .................................................. 37 2.3.10 me stolen memory accesses ................................................................. 37 2.3.11 i/o address space .............................................................................. 38 2.3.11.1 pci express* i/o address mapping.............................................. 38 2.3.12 mctp and kvm flows ........................................................................... 39 2.3.13 decode rules and cross-bridge address mapping .................................... 39 2.3.13.1 dmi interface decode rules ....................................................... 39 2.3.13.2 pci express* interface decode rules........................................... 42 2.3.13.3 legacy vga and i/o range decode rules..................................... 43 2.4 i/o mapped registers ........................................................................................ 46 2.5 pci device 0 function 0 configuration space re gisters........................................... 47 2.5.1 vid?vendor identification register ....................................................... 48 2.5.2 did?device identification register........ ................................................ 49 2.5.3 pcicmd?pci command register .......................................................... 49 2.5.4 pcists?pci status register ................................................................ 50 2.5.5 rid?revision identification register ...... ............................................... 52 2.5.6 cc?class code register ...................................................................... 52 2.5.7 hdr?header type register.................................................................. 53 2.5.8 svid?subsystem vendor identification re gister ..................................... 53 2.5.9 sid?subsystem identification register.... .............................................. 53 4 datasheet, volume 2 2.5.10 capptr?capabilities pointer register ............ ........... .......... ........... ........54 2.5.11 pxpepbar?pci express* egress port base address register .....................54 2.5.12 mchbar?host memory mapped register range base register ..................55 2.5.13 ggc?gmch graphics control register ...................................................55 2.5.14 deven?device enable register.............................................................57 2.5.15 pavpc?protected audio video path control register ................................59 2.5.16 dpr?dma protected range register ......................................................59 2.5.17 pciexbar?pci express* register range base address register ................60 2.5.18 dmibar?root complex register range base address register..................62 2.5.19 meseg_base?intel ? management engine base address register..............63 2.5.20 meseg_mask?intel ? management engine limit address register.............64 2.5.21 pam0?programmable attribute map 0 register .......................................65 2.5.22 pam1?programmable attribute map 1 register .......................................66 2.5.23 pam2?programmable attribute map 2 register .......................................67 2.5.24 pam3?programmable attribute map 3 register .......................................68 2.5.25 pam4?programmable attribute map 4 register .......................................69 2.5.26 pam5?programmable attribute map 5 register .......................................70 2.5.27 pam6?programmable attribute map 6 register .......................................71 2.5.28 lac?legacy access control register......................................................72 2.5.29 remapbase?remap base address register............................................76 2.5.30 remaplimit?remap limit address register ...........................................77 2.5.31 tom?top of memory register...............................................................77 2.5.32 touud?top of upper usable dram register ..........................................78 2.5.33 bdsm?base data of stolen memory register ..........................................79 2.5.34 bgsm?base of gtt stolen memory regist er ...........................................79 2.5.35 tsegmb?tseg memory base register ...................................................80 2.5.36 tolud?top of low usable dram register..............................................80 2.5.37 skpd?scratchpad data register ...........................................................81 2.5.38 capid0_a?capabilities a regi ster ......... ............ ........... .......... ......... ......82 2.5.39 capid0_b?capabilities b register .........................................................84 2.5.40 errsts?error status register .............................................................86 2.5.41 errcmd?error command register .......................................................87 2.5.42 smicmd?smi command register .........................................................88 2.5.43 scicmd?sci command register .........................................................88 2.6 pci device 1 function 0 configuration space re gisters ...........................................89 2.6.1 vid?vendor identification register........................................................90 2.6.2 did?device identification register ........................................................91 2.6.3 pcicmd?pci command register ...........................................................91 2.6.4 pcists?pci status register .................................................................93 2.6.5 rid?revision identification register ...... ................................................95 2.6.6 cc?class code register.......................................................................95 2.6.7 cl?cache line size register.................................................................95 2.6.8 hdr?header type register ..................................................................96 2.6.9 pbusn?primary bus number register ...................................................96 2.6.10 sbusn?secondary bus number register ...............................................96 2.6.11 subusn?subordinate bus number register ...........................................97 2.6.12 iobase?i/o base address register .......................................................97 2.6.13 iolimit?i/o limit address register ......................................................98 2.6.14 ssts?secondary status register ..........................................................98 2.6.15 mbase?memory base address register ............................................... 100 2.6.16 mlimit?memory limit address register............................................... 101 2.6.17 pmbase?prefetchable memory base address register............................ 102 2.6.18 pmlimit?prefetchable memory limit address register ........................... 103 2.6.19 pmbaseu?prefetchable memory base address upper register ................ 103 2.6.20 pmlimitu?prefetchable memory limit address upper register................ 104 2.6.21 capptr?capabilities pointer register ............ ........... .......... ........... ...... 104 datasheet, volume 2 5 2.6.22 intrline?interrupt line register ....................................................... 105 2.6.23 intrpin?interrupt pin register .......................................................... 105 2.6.24 bctrl?bridge control register .......................................................... 106 2.6.25 pm_capid?power management capabilities register ............................. 107 2.6.26 pm_cs?power management control/status register ............................. 108 2.6.27 ss_capid?subsystem id and vendor id capabilities register .......... ...... 110 2.6.28 ss?subsystem id and subsystem vendor id register........................... 110 2.6.29 msi_capid?message signaled interrup ts capability id regi ster ...... ....... 111 2.6.30 mc?message control register ............................................................ 112 2.6.31 ma?message address register ........................................................... 113 2.6.32 md?message data register ............................................................... 113 2.6.33 peg_capl?pci express-g capability list register ........ .......... ........... .... 114 2.6.34 peg_cap?pci expr ess-g capabilities register ......... ............ ........... ...... 114 2.6.35 dcap?device capabilities register.......... .......... ........... ........... ............ 115 2.6.36 dctl?device control register............................................................ 116 2.6.37 dsts?device status register............................................................. 117 2.6.38 lcap?link capabilities regi ster ............ ............ ........... ........... ............ 118 2.6.39 lctl?link control register ................................................................ 120 2.6.40 lsts?link status register................................................................. 122 2.6.41 slotcap?slot capabilities register ........ .......... ........... ........... ............ 123 2.6.42 slotctl?slot control register .......................................................... 125 2.6.43 slotsts?slot status register ........................................................... 127 2.6.44 rctl?root control register ............................................................... 129 2.6.45 rsts?root status register.................. .............................................. 130 2.6.46 dcap2?device capabilities 2 register ...... ................ .......... ........... ...... 131 2.6.47 dctl2?device control 2 register ....................................................... 132 2.6.48 lcap2?link capabilities 2 register ......... .......... ........... ........... ............ 133 2.6.49 lctl2?link control 2 register ........................................................... 133 2.6.50 lsts2?link status 2 register ............................................................ 135 2.7 pci device 1 function 0 extended configuratio n registers .................................... 136 2.7.1 pvccap1?port vc capability register 1 ... .......... ........... ........... ............ 137 2.7.2 pvccap2?port vc capability register 2 ... .......... ........... ........... ............ 137 2.7.3 pvcctl?port vc control register ....................................................... 138 2.7.4 vc0rcap?vc0 resource capability register ................ .......... ........... .... 139 2.7.5 vc0rctl?vc0 resource control register............................................. 140 2.7.6 vc0rsts?vc0 resource status register ............................................. 141 2.7.7 peg_tc?pci express* completion timeout register ............................. 141 2.7.8 eqctl0_1?lane 0/1 equalization control register ................................ 142 2.7.9 eqctl2_3?lane 2/3 equalization control register ................................ 144 2.7.10 eqctl4_5?lane 4/5 equalization control register ................................ 145 2.7.11 eqctl6_7?lane 6/7 equalization control register ................................ 146 2.7.12 eqctl8_9?lane 8/9 equalization control register ................................ 147 2.7.13 eqctl10_11?lane 10/11 equalization control register ......................... 148 2.7.14 eqctl12_13?lane 12/13 equalization control register ......................... 149 2.7.15 eqctl14_15?lane 14/15 equalization control register ......................... 150 2.7.16 eqcfg?equalization configuration register ......................................... 151 2.8 pci device 2 configuration space registers ........................................................ 153 2.8.1 vid2?vendor identification register ................................................... 154 2.8.2 did2?device identification register.................................................... 154 2.8.3 pcicmd2?pci command register....................................................... 155 2.8.4 pcists2?pci status register............................................................. 156 2.8.5 rid2?revision identification register.................................................. 157 2.8.6 cc?class code register .................................................................... 157 2.8.7 cls?cache line size register ............................................................ 158 2.8.8 mlt2?master latency timer register .................................................. 158 2.8.9 hdr2?header type register .............................................................. 158 6 datasheet, volume 2 2.8.10 gttmmadr?graphics translation table, memory mapped range address register .......................................................... 159 2.8.11 gmadr?graphics memory range address register................................ 160 2.8.12 iobar?i/o base address register....................................................... 161 2.8.13 svid2?subsystem vendor identification register .................................. 161 2.8.14 sid2?subsystem identification register .. ............................................ 162 2.8.15 romadr?video bios rom base address register ................................. 162 2.8.16 cappoint?capabilities pointer register .... ................ .......... ........... ...... 162 2.8.17 intrline?interrupt line register ......... .............................................. 163 2.8.18 intrpin?interrupt pin register .......................................................... 163 2.8.19 mingnt?minimum grant register ....................................................... 163 2.8.20 maxlat?maximum latency register ................................................... 164 2.8.21 msac?multi size aperture control register .......................................... 164 2.9 device 2 io registers ....................................................................................... 165 2.9.1 index?mmio address register ............................................................ 165 2.9.2 data?mmio data register.................................................................. 165 2.10 pci device 6 registers ..................................................................................... 166 2.10.1 vid?vendor identification register........ .............................................. 167 2.10.2 did?device identification register ........ .............................................. 168 2.10.3 pcicmd?pci command register ......................................................... 168 2.10.4 pcists?pci status register ............................................................... 171 2.10.5 rid?revision identification register ...... .............................................. 172 2.10.6 cc?class code register..................................................................... 173 2.10.7 cl?cache line size register............................................................... 173 2.10.8 hdr?header type register ................................................................ 173 2.10.9 pbusn?primary bus number register ................................................. 174 2.10.10 sbusn?secondary bus number register ............................................. 174 2.10.11 subusn?subordinate bus number register ......................................... 174 2.10.12 iobase?i/o base address register ..................................................... 175 2.10.13 iolimit?i/o limit address register .................................................... 175 2.10.14 ssts?secondary status register ........................................................ 176 2.10.15 mbase?memory base address register ............................................... 177 2.10.16 mlimit?memory limit address register............................................... 178 2.10.17 pmbase?prefetchable memory base address register............................ 179 2.10.18 pmlimit?prefetchable memory limit address register ........................... 180 2.10.19 pmbaseu?prefetchable memory base address upper register ................ 181 2.10.20 pmlimitu?prefetchable memory limit address upper register................ 182 2.10.21 capptr?capabilities pointer register ...... ............ ........... ........ ............. 183 2.10.22 intrline?interrupt line register ....................................................... 183 2.10.23 intrpin?interrupt pin register .......................................................... 184 2.10.24 bctrl?bridge control register ........................................................... 184 2.10.25 pm_capid?power management capabilitie s register ............ ........... ...... 186 2.10.26 pm_cs?power management control/status register .............................. 187 2.10.27 ss_capid?subsystem id and vendor id capabilities register ................ 189 2.10.28 ss?subsystem id and subsystem vendor id register ........................... 189 2.10.29 msi_capid?message signaled interru pts capability id regi ster ............. 190 2.10.30 mc?message control register............................................................. 190 2.10.31 ma?message address register............................................................ 191 2.10.32 md?message data register ................................................................ 192 2.10.33 peg_capl?pci express-g capability list register .............. ......... .......... 192 2.10.34 peg_cap?pci express-g capabilities register ...................................... 193 2.10.35 dcap?device capabilities register ........ ............ ........... .......... ............. 193 2.10.36 dctl?device control register ............................................................ 194 2.10.37 dsts?device status register ............................................................. 195 2.10.38 lcap?link capabilities regi ster .................. ........... ............ ........... ...... 196 2.10.39 lctl?link control register ................................................................ 198 datasheet, volume 2 7 2.10.40 lsts?link status register................................................................. 200 2.10.41 slotcap?slot capabilities register ........ .......... ........... ........... ............ 201 2.10.42 slotctl?slot control register .......................................................... 203 2.10.43 slotsts?slot status register ........................................................... 205 2.10.44 rctl?root control register ............................................................... 207 2.10.45 lcap2?link capabilities 2 register ......... .......... ........... ........... ............ 207 2.11 pci device 6 extended configuration registers.................................................... 208 2.11.1 pvccap1?port vc capability register 1 ... .......... ........... ........... ............ 209 2.11.2 pvccap2?port vc capability register 2 ... .......... ........... ........... ............ 209 2.11.3 pvcctl?port vc control register ....................................................... 210 2.11.4 vc0rcap?vc0 resource ca pability register.............. .......... ........... ...... 210 2.11.5 vc0rctl?vc0 resource control register............................................. 212 2.11.6 vc0rsts?vc0 resource status register ............................................. 213 2.11.7 rcldech?root complex link declaratio n enhanced ............................. 213 2.11.8 esd?element self description register................................................ 214 2.11.9 le1d?link entry 1 description register ............................................... 215 2.11.10 le1a?link entry 1 address register.................................................... 215 2.11.11 le1ah?link entry 1 address register.................................................. 216 2.11.12 apicbase?apic base address register ............................................... 216 2.11.13 apiclimit?apic base address limit register ....................................... 217 2.11.14 cmnrxerr?common rx error register ............................................... 217 2.11.15 pegtst?pci express* test modes register.......................................... 218 2.11.16 pegupdncfg?peg upconfig/dnconfig control register ......................... 218 2.11.17 bgfctl3?bgf control 3 register ....................................................... 219 2.11.18 eqpreset1_2?equalization preset 1/2 register ................................... 220 2.11.19 eqpreset2_3_4?equalization preset 2/3/4 register ............................. 220 2.11.20 eqpreset6_7?equalization preset 6/7 register ................................... 221 2.11.21 eqcfg?equalization configuration register ......................................... 221 2.12 direct media interface base address registers (dmibar)...................................... 222 2.12.1 dmivcech?dmi virtual channel enhanced capability register ............... 223 2.12.2 dmipvccap1?dmi port vc capability regi ster 1.......... .......... ........... .... 224 2.12.3 dmipvccap2?dmi port vc capability regi ster 2.......... .......... ........... .... 224 2.12.4 dmipvcctl?dmi port vc control register ........................................... 225 2.12.5 dmivc0rcap?dmi vc0 reso urce capability register .... .............. .......... 225 2.12.6 dmivc0rctl?dmi vc0 resource control register ................................ 226 2.12.7 dmivc0rsts?dmi vc0 resource status register ................................. 227 2.12.8 dmivc1rcap?dmi vc1 reso urce capability register .... .............. .......... 227 2.12.9 dmivc1rctl?dmi vc1 resource control register ................................ 228 2.12.10 dmivc1rsts?dmi vc1 resource status register ................................. 229 2.12.11 dmivcprcap?dmi vcp reso urce capability register.... .......... ........... .... 229 2.12.12 dmivcprctl?dmi vcp resource control register ................................ 230 2.12.13 dmivcprsts?dmi vcp resource status register ................................. 231 2.12.14 dmivcmrcap?dmi vcm resource capability register ........................... 231 2.12.15 dmivcmrctl?dmi vcm resource control register ............................... 232 2.12.16 dmivcmrsts?dmi vcm resource status register................................ 233 2.12.17 dmircldech?dmi root complex link declaration register ................... 233 2.12.18 dmiesd?dmi element self description register ................................... 234 2.12.19 dmile1d?dmi link entry 1 description register................................... 235 2.12.20 dmile1a?dmi link entry 1 address register........................................ 236 2.12.21 dmilue1a?dmi link upper entry 1 address register ............................ 236 2.12.22 dmile2d?dmi link entry 2 description register................................... 237 2.12.23 dmile2a?dmi link entry 2 address register........................................ 238 2.12.24 lcap?link capabilities regi ster ............ ............ ........... ........... ............ 238 2.12.25 lctl?link control register ................................................................ 239 2.12.26 lsts?dmi link status register .......................................................... 240 2.12.27 lctl2?link control 2 register ........................................................... 241 8 datasheet, volume 2 2.12.28 lsts2?link status 2 register............................................................. 243 2.13 mchbar registers in memory controller?channe l 0 registers............................... 244 2.13.1 tc_dbp_c0?timing of ddr ? bin parameters register .......................... 245 2.13.2 tc_rap_c0?timing of ddr ? regular access parameters register .......... 246 2.13.3 sc_io_latency_c0?io latency configuration register ......................... 247 2.13.4 tc_srftp_c0?self refresh timing parameters register ......................... 247 2.13.5 pm_pdwn_config_c0?power-down configuration register ...................... 248 2.13.6 eccerrlog0_c0?ecc error log 0 register ......................................... 249 2.13.7 eccerrlog1_c0?ecc error log 1 register ......................................... 250 2.13.8 tc_rfp_c0?refresh parameters register............................................. 250 2.13.9 tc_rftp_c0?refresh timing parameters register................................. 251 2.14 mchbar registers in memory controller ? channel 1 ........................................... 252 2.14.1 tc_dbp_c1?timing of ddr ? bin parameters register .......................... 252 2.14.2 tc_rap_c1?timing of ddr ? regular access parameters register .......... 253 2.14.3 sc_io_latency_c1?io latency configuration register ......................... 254 2.14.4 pm_pdwn_config_c1?power-down configuration register ..................... 255 2.14.5 eccerrlog0_c1?ecc error log 0 register ......................................... 256 2.14.6 eccerrlog1_c1?ecc error log 1 register ......................................... 257 2.14.7 tc_rfp_c1?refresh parameters register............................................. 257 2.14.8 tc_rftp_c1?refresh timing parameters register................................. 258 2.14.9 tc_srftp_c1?self refresh timing parameters register ......................... 258 2.15 mchbar registers in memory controller ? integrated memory peripheral hub (imph) .......................................................... 259 2.15.1 crdtctl3?credit control 3 register ................................................... 259 2.15.2 crdtctl4?credit control 4 register ................................................... 260 2.16 mchbar registers in memory controller ? common ............................................. 261 2.16.1 mad_chnl?address decoder channel configuration register ................. 261 2.16.2 mad_dimm_ch0?address decode channel 0 register ............................ 262 2.16.3 mad_dimm_ch1?address decode channel 1 register ............................ 263 2.16.4 pm_sref_config?self refresh configuration register............................. 264 2.17 memory controller mmio registers broadcast gr oup registers............................... 265 2.17.1 pm_pdwn_config?power-down configuration register ........................... 266 2.17.2 eccerrlog0?ecc error log 0 register .............................................. 267 2.17.3 eccerrlog1?ecc error log 1 register .............................................. 267 2.17.4 pm_cmd_pwr?power management command power register ................ 268 2.17.5 pm_bw_limit_config?bw limit configuration register ....................... 268 2.18 integrated graphics vtd remapping engine registers .......................................... 269 2.18.1 ver_reg?version register ................................................................ 270 2.18.2 cap_reg?capability register .......... ........... ........... ............ ........... ...... 271 2.18.3 ecap_reg?extended capability register .... ................ .......... ........... .... 275 2.18.4 gcmd_reg?global command register ................................................ 276 2.18.5 gsts_reg?global status register ...................................................... 280 2.18.6 rtaddr_reg?root-entry table address register ................................. 281 2.18.7 ccmd_reg?context command register .............................................. 282 2.18.8 fsts_reg?fault status register ........................................................ 284 2.18.9 fectl_reg?fault event control register ............................................. 286 2.18.10 fedata_reg?fault event data register .............................................. 287 2.18.11 feaddr_reg?fault event address register ......................................... 287 2.18.12 feuaddr_reg?fault event upper address register .............................. 287 2.18.13 aflog_reg?advanced fault log register ............................................ 288 2.18.14 pmen_reg?protected memory enable register ..................................... 289 2.18.15 plmbase_reg?protected low-memory base register ............................ 290 2.18.16 plmlimit_reg?protected low-memory limit register ........................... 291 2.18.17 phmbase_reg?protected high-memory base register .......................... 292 2.18.18 phmlimit_reg?protected high-memory limit register .......................... 293 2.18.19 iqh_reg?invalidation queue head register......................................... 294 datasheet, volume 2 9 2.18.20 iqt_reg?invalidation queue tail register........................................... 294 2.18.21 iqa_reg?invalidation queue address register .................................... 295 2.18.22 ics_reg?invalidation completion status register ................................ 295 2.18.23 iectl_reg?invalidation event control register.................................... 296 2.18.24 iedata_reg?invalidation event data register..................................... 297 2.18.25 ieaddr_reg?invalidation event address register................................ 297 2.18.26 ieuaddr_reg?invalidation event upper address register..................... 298 2.18.27 irta_reg?interrupt remapping table ad dress register........................ 298 2.18.28 iva_reg?invalidate address register ................................................. 299 2.18.29 iotlb_reg?iotlb invalidate register ................................................ 300 2.18.30 frcdl_reg?fault recording low register........................................... 302 2.18.31 frcdh_reg?fault recording high register ......................................... 303 2.18.32 vtpolicy?dma remap engine policy cont rol register........................... 304 2.19 pcu mchbar registers .................................................................................... 305 2.19.1 mem_trml_estimation_config?memory thermal estimation configuration register.. .......................................... 306 2.19.2 mem_trml_thresholds_config?memory thermal thresholds configuration register ........................................... 307 2.19.3 mem_trml_status_report?memory thermal status report register ....................................................................... 308 2.19.4 mem_trml_temperature_report?memory thermal temperature report register.................................................. 309 2.19.5 mem_trml_interrupt?memory thermal interrupt register ............................................................................. 309 2.19.6 gt_perf_status?gt performance status register .............................. 310 2.19.7 rp_state_limits?rp-state limitations re gister ................................. 310 2.19.8 rp_state_cap?rp state capability register .......... ............ ........... ...... 311 2.19.9 pcu_mmio_freq_clipping_cause_status register........................... 311 2.19.10 pcu_mmio_freq_clipping_cause_log register ................................ 313 2.19.11 sskpd?sticky scratchpad data register ............................................. 315 2.20 pxpepbar registers ........................................................................................ 317 2.20.1 epvc0rctl?ep vc 0 resource control register.................................... 317 2.21 default peg/dmi vtd remapping engine registers .............................................. 318 2.21.1 ver_reg?version register ................................................................ 319 2.21.2 cap_reg?capability register.. ........... .......... ........... .......... ........... ...... 320 2.21.3 ecap_reg?extended capability register .... ................ .......... ........... .... 324 2.21.4 gcmd_reg?global command register................................................ 325 2.21.5 gsts_reg?global status register.......... ............................................ 329 2.21.6 rtaddr_reg?root-entry table address register................................. 330 2.21.7 ccmd_reg?context command register.............................................. 331 2.21.8 fsts_reg?fault status register ........................................................ 333 2.21.9 fectl_reg?fault event control register............................................. 335 2.21.10 fedata_reg?fault event data register.............................................. 336 2.21.11 feaddr_reg?fault event address register ......................................... 336 2.21.12 feuaddr_reg?fault event upper address register.............................. 336 2.21.13 aflog_reg?advanced fault log register ........................................... 337 2.21.14 pmen_reg?protected memory enable register..................................... 338 2.21.15 plmbase_reg?protected low-memory base register ........................... 339 2.21.16 plmlimit_reg?protected low-memory limit register........................... 340 2.21.17 phmbase_reg?protected high-memory base register .......................... 341 2.21.18 phmlimit_reg?protected high-memory limit register ......................... 342 2.21.19 iqh_reg?invalidation queue head register ........................................ 343 2.21.20 iqt_reg?invalidation queue tail register........................................... 343 2.21.21 iqa_reg?invalidation queue address register .................................... 344 2.21.22 ics_reg?invalidation completion status register ................................ 345 2.21.23 iectl_reg?invalidation event control register.................................... 345 2.21.24 iedata_reg?invalidation event data register..................................... 346 10 datasheet, volume 2 2.21.25 ieaddr_reg?invalidation event address register ................................ 347 2.21.26 ieuaddr_reg?invalidation event upper address register ..................... 347 2.21.27 irta_reg?interrupt remapping table address register ........................ 348 2.21.28 iva_reg?invalidate address register.................................................. 349 2.21.29 iotlb_reg?iotlb invalidate register................................................. 350 figures 2-1 system address range example ..........................................................................19 2-2 dos legacy address range ................................................................................20 2-3 main memory address range...............................................................................22 2-4 pci memory address range ................................................................................26 2-5 case 1 ? less than 4 gb of physical memory (no remap) ........................................31 2-6 case 2 ? greater than 4 gb of physical memory .....................................................32 2-7 example: dmi upstream vc0 memory map............................................................41 2-8 peg upstream vc0 memory map..........................................................................43 tables 2-1 register attributes and terminology.....................................................................15 2-2 register attribute modifiers .................................................................................16 2-3 pci devices and functions ..................................................................................16 2-4 smm regions ....................................................................................................37 2-5 igd frame buffer accesses .................................................................................44 2-6 igd vga i/o mapping ........................................................................................44 2-7 vga and mda i/o transaction mapping ................................................................45 2-8 pci device 0, function 0 configuration spac e register address map .........................47 2-9 ci device1 function 0 configuration space regi ster address map.............................89 2-10 pci device 1 function 0 extended configuration register address map ................... 136 2-11 pci device 2 configuration space register address map ....................................... 153 2-12 device 2 io register address map...................................................................... 165 2-13 pci device 6 register address map .................................................................... 166 2-14 pci device 6 extended configuration register address map ................................... 208 2-15 dmibar register address map........................................................................... 222 2-16 mchbar registers in memory controller ? channel 0 register address map............. 244 2-17 mchbar registers in memory controller ? channel 1 register address map............. 252 2-18 mchbar registers in memory cont roller ?integrated memory peripheral hub (imph) register address map...................................................................... 259 2-19 mchbar registers in memory controller ? common register address map .............. 261 2-20 memory controller mmio registers broadcast group register address map.............. 265 2-21 integrated graphics vtd remapping engine register address map ......................... 269 2-22 pcu mchbar register address map ................................................................... 305 2-23 pxpepbar address map .................................................................................... 317 2-24 default peg/dmi vtd remapping engine regist er address map.............................. 318 datasheet, volume 2 11 revision history revision number description revision date 001 initial release may 2012 12 datasheet, volume 2 datasheet, volume 2 13 introduction 1 introduction this is volume 2 of the datasheet for the following products: ?intel ? xeon ? processor e3-1200 v2 product family the processor contains one or more pci devi ces within a single physical component. the configuration registers for these devices are mapped as devices residing on the pci bus assigned for the processor socket. this document describes the configuration space registers or device-specific control and status registers (csrs) only. this document does not include model specific registers (msrs). note: throughout this document, intel ? xeon ? processor e3-1200 v2 product family may be referred to simply as ?processor?. note: throughout this document, the intel ? c200/c216 series chipset platform controller hub may also be referred to as ?pch?. note: the term ?srv? refers to server platform s. the term ?ws? refers to workstation platforms. note: pci express* hot-plug is not supported on the processor. introduction 14 datasheet, volume 2 datasheet, volume 2 15 processor configuration registers 2 processor configuration registers this chapter contains the following: ? register terminology ? pci devices and functions on processor ? system address map ? processor register introduction ? detailed register bit descriptions 2.1 register terminology table 2-1 lists the register-related terminology and access attributes that are used in this document. table 2-2 provides the attribute modifiers. table 2-1. register attr ibutes and terminology item description ro read only: these bits can only be read by software, writes have no effect. the value of the bits is determined by the hardware only. rw read / write: these bits can be read and written by software. rw1c read / write 1 to clear: these bits can be read and cleared by software. writing a '1' to a bit will clear it, while writing a '0' to a bit ha s no effect. hardware sets these bits. rw0c read / write 0 to clear: these bits can be read and cleared by software. writing a ?0? to a bit will clear it, while writing a ?1? to a bit ha s no effect. hardware sets these bits. rw1s read / write 1 to set: these bits can be read and set by software. writing a ?1? to a bit will set it, while writing a ?0? to a bit has no effect. hardware clears these bits. rsvdp reserved and preserved: these bits are reserved for future rw implementations and their value must not be modified by software. when writing to these bits, software must preserve the value read. when software updates a register that has rsvdp fields, it must read the register value first so that the appropriate merge between the rsvdp and updated fields will occur. rsvdz reserved and zero: these bits are reserved for future rw1c implementations. software must use 0 for writes. wo write only: these bits can only be written by software, reads return zero. note: use of this attribute type is deprecated and can only be used to describe bits without persistent state. rc read clear: these bits can only be read by software, bu t a read causes the bits to be cleared. hardware sets these bits. note: use of this attribute type is only allowed on legacy functions, as side-effects on reads are not desirable. rsw1c read set / write 1 to clear: these bits can be read and cleared by software. reading a bit will set the bit to ?1?. writing a ?1? to a bit will clear it, while writing a ?0? to a bit has no effect. rcw read clear / write: these bits can be read and written by software, but a read causes the bits to be cleared. note: use of this attribute type is only allowed on legacy functions, as side-effects on reads are not desirable. processor configuration registers 16 datasheet, volume 2 2.2 pci devices and functions note: not all devices are enabled in all configurations. table 2-2. register attribute modifiers attribute modifier applicable attribute description s ro (w/ -v) sticky : these bits are only re-initialized to their reset value by a "power good reset". note: does not apply to ro (constant) bits. rw rw1c rw1s -k rw key: these bits control the ability to write other bits (identified with a 'lock' modifier) -l rw lock: hardware can make these bits "read only" using a separate configuration bit or other logic. note: mutually exclusive with 'once' modifier. wo -o rw once: after reset, these bits can only be written by software once, after which they become "read only". note: mutually exclusive with 'lock' modifier and does not make sense with 'variant' modifier. wo -fw ro firmware write: the value of these bits can be updated by firmware (pcu, tap, and so on). -v ro variant: the value of these bits can be updated by hardware. note: rw1c and rc bits are variant by definition and therefore do not need to be modified. table 2-3. pci devi ces and functions description did device function dram controller 0158h 0 0 pci express controller 0151h 1 0 pci express controller 0155h 1 1 pci express controller 0159h 1 2 integrated graphics device 015ah 2 0 pci express controller 015dh 6 0 datasheet, volume 2 17 processor configuration registers 2.3 system address map the processor supports 512 gb (39 bit) of addressable memory space and 64 kb+3 of addressable i/o space. this section focuses on how the memory space is partitioned and the use of the separate memory regions. i/o address space has simpler mapping and is explained near the end of this section. the processor supports peg port upper prefetch able base/limit registers. this allows the peg unit to claim i/o accesses above 32 bit. addressing of greater than 4 gb is allowed on either the dmi interface or pci express interface. the processor supports a maximum of 32 gb of dram. no dram me mory will be accessible above 32 gb. dram capacity is limited by the num ber of address pins available. there is no hardware lock to stop someone from inserting more memory than is addressable. when running in internal graphics mode , processor initiated tilex/tiley/linear reads/writes to gmadr range are supporte d. write accesses to gmadr linear regions are supported from both dmi and peg. gmadr write accesses to tilex and tiley regions (defined using fence registers) are not su pported from dmi or the peg port. gmadr read accesses are not supported from either dmi or peg. in the following sections, it is assumed that all of the compatibility memory ranges reside on the dmi interface. the exception to this rule is vga ranges, which may be mapped to pci express*, dmi, or to the internal graphics device (igd). in the absence of more specific references, cycle description s referencing pci should be interpreted as the dmi interface/pci, while cycle descrip tions referencing pci express or igd are related to the pci express bus or the in ternal graphics device respectively. the processor does not remap apic or any other memory spaces above tolud (top of low usable dram). the tolud register is se t to the appropriate value by bios. the remapbase/remaplimit registers remap logical accesses bound for addresses above 4 gb onto physical addresses that fall within dram. the address map includes a number of programmable ranges: ? device 0: ? pxpepbar ? pxp egress port registers. (4 kb window) ? mchbar ? memory mapped range for inte rnal mch registers. (32 kb window) ? dmibar ?this window is used to access registers associated with the processor/pch serial interconnect (d mi) register memory range. (4 kb window) ? ggc.gms ? graphics mode select. used to select the amount of main memory that is pre-allocated to support the inte rnal graphics device in vga (non-linear) and native (linear) modes. (0?1 gb options). ? ggc.ggms ? gtt graphics memory size. us ed to select the amount of main memory that is pre-allocated to support the internal graphics translation table. (0?2 mb options). for each of the following five device functions: ? device 1, function 0: (pcie x16 controller) ? device 1, function 1: (pcie x8 controller) ? device 1, function 2: (pcie x4 controller) processor configuration registers 18 datasheet, volume 2 ? device 6, function 0: (pcie x4 controller) ? mbase/mlimit ? pci express port non- prefetchable memory access window. ? pmbase/pmlimit ? pci express port prefetchable memory access window. ? pmubase/pmulimit ? pci express port upper prefetchable memory access window ? iobase/iolimit ? pci express port i/o access window. ? device 2, function 0: (integrated graphics device (igd)) ? iobar ? i/o access window for internal graphics. through this window address/data register pair, using i/o semantics, the igd and internal graphics instruction port registers can be accessed. note, this allows accessing the same registers as gttmmadr. the iobar can be used to issue writes to the gttmmadr or the gtt table. ? gmadr ? internal graphics translation window (128 mb, 256 mb, 512 mb window). ? gttmmadr ? this register requests a 4 mb allocation for combined graphics translation table modification range and memory mapped range. gttadr will be at gttmmadr + 2 mb while the mmio base address will be the same as gttmmadr. the rules for the above programmable ranges are: 1. for security reasons, the processor will now positively decode (ffe0_0000h to ffff_ffffh) to dmi. this ensures the b oot vector and bios execute off pch. 2. all of these ranges must be unique and non-overlapping. it is the bios or system designers' responsibility to limit me mory population so that adequate pci, pci express, high bios, pci express me mory mapped space, and apic memory space can be allocated. 3. in the case of overlapping ranges with memory, the memory decode will be given priority. this is an intel txt requirement. it is necessary to get intel txt protection checks, avoiding potential attacks. 4. there are no hardware interlocks to prev ent problems in the case of overlapping ranges. 5. accesses to overlapped ranges may produce indeterminate results. 6. the only peer-to-peer cycles allowed below the top of low usable memory (register tolud) are dmi interface to pc i express vga range writes. note that peer to peer cycles to the internal graphics vga range are not supported. figure 2-1 shows the system memory addr ess map in a simplified form. datasheet, volume 2 19 processor configuration registers 2.3.1 legacy address range this area is divided into the following address regions: ? 0?640 kb ? dos area ? 640?768 kb ? legacy video buffer area ? 768?896 kb in 16 kb sections (total of 8 sections) ? expansion area ? 896?960 kb in 16 kb sections (total of 4 sections) ? extended system bios area ? 960 kb?1 mb memory ? system bios area figure 2-1. system address range example main memory add range os visible < 4 gb pci memory add. range (subtractively decoded to dmi) host/system view physical memory (dram controller view) tseg 0 0 tseg base gfx stolen (0-256 mb) me-uma tom gfx gtt stolen base meseg base 1 mb aligned 1 mb aligned os invisible reclaim 1 mb aligned for reclaim 1 mb aligned 4 gb fec0_0000 1 mb aligned touud base 1 mb aligned gfx gtt stolen (0-2 mb) gfx stolen base 1 mb aligned tseg (0-8 mb) legacy add. range 1 mb main memory address range os visible > 4 gb main memory reclaim add range reclaim base reclaim limit = reclaim base + x 1 mb aligned pci memory add. range (subtractively decoded to dmi) 1 mb aligned 512 gb x flash, apic intel ? txt (20 mb) tolud base processor configuration registers 20 datasheet, volume 2 2.3.1.1 dos range (0h?9_ffffh) the dos area is 640 kb (0000_0000h?0009_ffffh) in size and is always mapped to the main memory controlled by the memory controller. 2.3.1.2 legacy video area (a_0000h?b_ffffh) the legacy 128 kb vga memory range, frame buffer, (000a_0000h?000b_ffffh) can be mapped to igd (device 2), to pci express (device 1 or device 6), and/or to the dmi interface. the appropriate mapping depend s on which devices are enabled and the programming of the vga steering bits. based on the vga steering bits, priority for vga mapping is constant. the processor always decodes internally mapped devices first. non-smm-mode processor accesses to this range are considered to be to the video buffer area as described above. the processor always positively decodes internally mapped devices, namely the igd and pci express*. subsequent decoding of regions mapped to pci express or the dmi interface depends on the legacy vga config uration bits (vga enable & mdap). this region is also the default for smm space. figure 2-2. dos legacy address range expansion area 128 kb (16kbx8) 000c_0000h 000d_ffffh 896 kb extended system bios (lower) 64 kb (16kbx4) 000e_0000h 000e_ffffh 960 kb legacy video area (smm memory) 128 kb 000a_0000h 000b_ffffh 768 kb dos area 0000_0000h 0009_ffffh 640 kb system bios (upper) 64 kb 000f_0000h 000f_ffffh 1 mb datasheet, volume 2 21 processor configuration registers compatible smram address range (a_0000h?b_ffffh) when compatible smm space is enabled, s mm-mode processor accesses to this range route to physical system dram at 000a_0000h?000b_ffffh. pci express and dmi originated cycles to enable smm space are not allowed and are considered to be to the video buffer area, if igd is not enabled as the vga device. dmi initiated writes cycles are attempted as peer writes cycles to a vga enabled pcie port. monochrome adapter (mda) range (b_0000h?b_7fffh) legacy support requires the ability to have a second graphics controller (monochrome) in the system. accesses in the standard vga range are forwarded to igd, pci express*, or the dmi interface (dependi ng on configuration bits). since the monochrome adapter may be mapped to any of these devices, the processor must decode cycles in the mda range (000b_0000h ?000b_7fffh) and forward either to igd, pci express*, or the dmi interface. this capability is controlled by the vga steering bits and the legacy configuration bit (mdap bit). in addition to the memory range b0000h to b7fffh, the processor decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh and forwards them to the either igd, pci express*, and/or the dmi interface. peg 16-bit vga decode the pci to pci bridge architecture specification revision 1.2 , it is required that 16-bit vga decode be a feature. when 16-bit vga decode is disabled, the decode of vga i/o addresses is performed on 10 lower bits only, essentially mapping also the aliases of the defined i/o addresses. 2.3.1.3 pam (c_0000h?f_ffffh) the 13 sections from 768 kb to 1 mb comprise what is also known as the pam memory area. each section has read enable and write enable attributes. the pam registers are mapped in device 0 configuration space. ? isa expansion area (c_0000h?d_ffffh) ? extended system bios area (e_0000h?e_ffffh) ? system bios area (f_0000h?f_ffffh) the processor decodes the core request; then routes to the appropriate destination (dram or dmi). snooped accesses from pci express or dmi to this region are snooped on processor caches. non-snooped accesses from pci express or dm i to this region are always sent to dram. graphics translated requests to this region are not allowed. if such a mapping error occurs, the request will be routed to c_0000. writes will have the byte enables de- asserted. processor configuration registers 22 datasheet, volume 2 2.3.2 main memory addres s range (1 mb ? tolud) this address range extends from 1 mb to the top of low usable physical memory that is permitted to be accessible by the processo r (as programmed in the tolud register). the processor will route all addresses within th is range to the dram unless it falls into the optional tseg, optional isa hole, or optional igd stolen vga memory. 2.3.2.1 isa hole (15 mb ? 16 mb) the isa hole is enabled in the legacy access control register in device 0 configuration space. if no hole is created, the processor will route the request to dram. if a hole is created, the processor will route the request to dmi, since the request does not target dram. graphics translated requests to the range will always route to dram. figure 2-3. main memory address range main memory isa hole (optional) dos compatibility memory 0h flash ffff_ffffh 00f0_0000h 15mb 16mb 0100_0000h 0mb tolud apic main memory 0010_0000h 1mb igd intel ? txt pci memory range 4 gb max contains: dev 0, 1, 2, 6, 7 bars & pch/pci ranges tseg iggtt dpr tseg_base datasheet, volume 2 23 processor configuration registers 2.3.2.2 tseg for processor initiated transactions, the pr ocessor relies on correct programming of smm range registers (smrr) to enforce tseg protection. tseg is below igd stolen memory, which is at the top of low usable physical memory (tolud). bios will calculate and program the tseg base in device 0 (tsegmb), used to protect this region from dma access. calculation is: tsegmb = tolud ? dsm size ? gsm size ? tseg size smm-mode processor accesses to enabled tseg access the physical dram at the same address. when the extended smram space is enabled, processor accesses to the tseg range without smm attribute or without wb attribute are handled by the processor as invalid accesses. non-processor originated accesses are not allowed to smm space. pci express*, dmi, and internal graphics originated cycle to enabled smm space are handled as invalid cycle type with reads and writes to locati on c_0000h and byte enables turned off for writes. 2.3.2.3 protected memory range (pmr) ? (programmable) for robust and secure launch of the mvmm, the mvmm code and private data needs to be loaded to a memory region protected from bus master accesses. support for the protected memory region is required for dma-remapping hardware implementations on platforms supporting intel txt, and is opti onal for non-intel txt platforms. since the protected memory region needs to be enabled before the mvmm is launched, hardware must support enabling of the protected me mory region independently from enabling the dma-remapping hardware. as part of the secure launch process, the sinit-ac module verifies the protected memory regions are properly configured an d enabled. once launched, the mvmm can setup the initial dma-remapping structures in protected memory (to ensure they are protected while being setup) before enabling the dma-remapping hardware units. to optimally support platform configurations supporting varying amounts of main memory, the protected memory region is defined as two non-overlapping regions: ? protected low-memory region : this is defined as the protected memory region below 4 gb to hold the mvmm code/priva te data, and the in itial dma-remapping structures that control dma to host physical addresses below 4 gb. dma- remapping hardware implementations on platforms supporting intel txt are required to support protected low-memory region5. ? protected high-memory region : this is defined as a variable sized protected memory region above 4 gb, enough to ho ld the initial dma-remapping structures for managing dma accesses to addresses above 4 gb. dma-remapping hardware implementations on platforms supporting intel txt are required to support protected high-memory region6, if the platform supports main memory above 4 gb. once the protected low/high memory region registers are configured, bus master protection to these regions is enabled thro ugh the protected memory enable register. for platforms with multiple dma-remapp ing hardware units, each of the dma- remapping hardware units must be config ured with the same protected memory regions and enabled. processor configuration registers 24 datasheet, volume 2 2.3.2.4 dram protected range (dpr) this protection range only ap plies to dma accesses and gmadr translations. it serves a purpose of providing a memory range that is only accessible to processor streams. the dpr range works independent of any othe r range, including the pmrc checks in vtd. it occurs post any vtd translation. th erefore, incoming cycles are checked against this range after the vtd translation and faulted if they hit this protected range, even if they passed the vtd translation. the system will set up: ? 0 to (tseg_base ? dpr size ? 1) for dma traffic ? tseg_base to (tseg_base ? dpr size) as no dma. after some time, software could request more space for not allowing dma. it will get some more pages and make sure there are no dma cycles to the new region. dpr size is changed to the new value. when it does this, there should not be any dma cycles going to dram to the new region. if there were cycles from a rogue device to the new region, then those could use the previous decode until the new decode can ensure pv. no flushing of cycles is required. on a clock by clock basis proper decode with the previous or new decode needs to be ensured. all upstream cycles from 0 to (tseg_base ? 1 ? dpr size), and not in the legacy holes (vga), are decoded to dram. because bus master cycles can occur when the dpr size is changed, the dpr size needs to be treated dynamically. 2.3.2.5 pre-allocated memory voids of physical addresses that are not accessible as general system memory and reside within system memory address range (< tolud) are created for smm-mode, legacy vga graphics compatibility, and graphics gtt stolen memory. it is the responsibility of bios to pr operly initialize these regions . 2.3.2.6 graphics stolen spaces 2.3.2.6.1 gtt stolen space (gsm) gsm is allocated to store the graphics (gfx) translation table entries. gsm always exists regardless of vt-d as long as internal graphics is enabled. this space is allocated to store accesses as page tabl e entries are getting updated through virtual gttmmadr range. hardware is responsible to map ptes into this physical space. direct accesses to gsm are not allowed; only hardware translations and fetches can be directed to gsm. datasheet, volume 2 25 processor configuration registers 2.3.2.7 intel ? management engine (intel ? me) uma intel me (the amt intel management engi ne) can be allocated uma memory. intel mememory is ?stolen? from the top of the host address map. the intel me stolen memory base is calculated by subtracting the amount of memory stolen by the intel management engine from tom. only intel me can access this space; it is not accessible by or coherent with any processor side accesses. 2.3.3 pci memory addres s range (tolud ? 4 gb) this address range, from the top of low usable dram (tolud) to 4 gb is normally mapped to the dmi interface. device 0 exceptions are: 1. addresses decoded to the egress port registers (pxpepbar) 2. addresses decoded to the memory mapped range for internal mch registers (mchbar) 3. addresses decoded to the registers associated with the mch/pch serial interconnect (dmi) register memory range (dmibar) for each pci express port, there are two exceptions to this rule: 1. addresses decoded to the pci express memory window defined by the mbase, mlimit, registers are ma pped to pci express. 2. addresses decoded to the pci express prefetchable memory window defined by the pmbase, pmlimit, registers are mapped to pci express in integrated graphics configurations, there are exceptions to this rule: 1. addresses decoded to the internal graphics translation window (gmadr) 2. addresses decoded to the internal graphics translation table or igd registers (gttmmadr) in a vt enabled configuration, th ere are exceptions to this rule: 1. addresses decoded to the memory mappe d window to graphics vt remap engine registers (gfxvtbar) 2. addresses decoded to the memory mapped window to dmi vc1 vt remap engine registers (dmivc1bar) 3. addresses decoded to the memory mapped window to peg/dmi vc0 vt remap engine registers (vtdpvc0bar) 4. tcm accesses (to intel me stolen memory) from pch do not go through vt remap engines. some of the mmio bars may be mapped to this range or to the range above touud. there are sub-ranges within the pci memory address range defined as apic configuration space, msi interrupt spac e, and high bios address range. the exceptions listed above for internal graphics and the pci express ports must not overlap with these ranges. processor configuration registers 26 datasheet, volume 2 2.3.3.1 apic configuration space (fec0_0000h ? fecf_ffffh) this range is reserved for apic configuratio n space. the i/o apic(s) usually reside in the pch portion of the chipset, but may also exist as stand-alone components like pxh. the ioapic spaces are used to communicate with ioapic interrupt controllers that may be populated in the system. since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. processor accesses to the default ioapic region (fec0_0000h to fec7_ffffh) are always forwarded to dmi. the processor optionally supports additi onal i/o apics behind the pci express* ?graphics? port. when enabled using the apic_base and apic_limit registers (mapped pci express* configuration space offset 240h and 244h), the pci express* port(s) will positively decode a subset of the apic configuration space. figure 2-4. pci memory address range dmi interface (subtractive decode) fef0_0000h 4 gb ? 2 mb msi interrupts fee0_0000h pci express* configuration space e000_0000h high bios ffe0_0000h ffff_ffffh 4 gb 4 gb ? 17 mb dmi interface (subtractive decode) fed0_0000h 4 gb ? 18 mb local (cpu) apic fec8_0000h 4 gb ? 19 mb i/o apic fec0_0000h 4 gb ? 20 mb dmi interface (subtractive decode) f000_0000h 4 gb ? 256 mb possible address range/ size (not ensured) 4 gb ? 512 mb dmi interface (subtractive decode) tolud bars, internal graphics ranges, pci express* port, chapadr could be here. datasheet, volume 2 27 processor configuration registers memory requests to this range would then be forwarded to the pci express* port. this mode is intended for the entry workstatio n/server sku of the mch, and would be disabled in typical desktop systems. when disabled, any access within entire apic configuration space (fec0_0000h to fecf_ffffh) is forwarded to dmi. 2.3.3.2 hseg (feda_0000h ? fedb_ffffh) this decode range is not suppor ted on the processor platform. 2.3.3.3 msi interrupt memory space (fee0_0000 ? feef_ffff) any pci express* or dmi device may issue a memory write to 0feex_xxxxh. this memory write cycle does not go to dram. the system agent will forward this memory write along with the data to the processor as an interrupt message transaction. 2.3.3.4 high bios area for security reasons, the processor will positively decode this range to dmi. this positive decode will ensure any ov erlapping ranges will be ignored. the top 2 mb (ffe0_0000h?ffff_ffffh) of the pci memory address range is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. the processor begins execution from the high bios after reset. this region is positively decoded to dmi . the actual address space required for the bios is less than 2 mb but the minimum processor mtrr range for this region is 2 mb so that full 2 mb must be considered. 2.3.4 main memory address space (4 gb to touud) the processor supports 39-bit addressing. the maximum main memory size supported is 32 gb total dram memory. a hole between tolud and 4 gb occurs when main memory size approaches 4 gb or larger. as a result, tom, and touud registers an d remapbase/remaplimit registers become relevant. the remap configuration registers exist to remap lost main memory space. the greater than 32 bit remap handling will be handled similar to other mchs. upstream read and write accesses above 39-b it addressing will be treated as invalid cycles by peg and dmi. top of memory (tom) the ?top of memory? (tom) register reflects the total amount of populated physical memory. this is not necessarily the highest main memory address (holes may exist in main memory address map due to addresse s allocated for memory mapped i/o above tom). the intel management engine (me) stolen si ze register reflects the total amount of physical memory stolen by the intel management engine. the intel me stolen memory is located at the top of physical memory. the intel me stolen memory base is calculated by subtracting the amount of memory stol en by the intel management engine from tom. processor configuration registers 28 datasheet, volume 2 top of upper usable dram (touud) the top of upper usable dram (touud) register reflects the total amount of addressable dram. if remap is disabled, touud will reflect tom minus intel management engine stolen size. if remap is enabled, then it will reflect the remap limit. note: when there is more than 4 gb of dram and reclaim is enabled, the reclaim base will be the same as tom minus intel me stolen me mory size to the nearest 1 mb alignment (shown in the following case 2). top of low usable dram (tolud) tolud register is restricted to 4 gb memo ry (a[31:20]), but the processor can support up to 32 gb, limited by dram pins. for physical memory greater than 4 gb, the touud register helps identify the address range in between the 4 gb boundary and the top of physical memory. this identifies memory that can be directly accessed (including remap address calculation), which is useful for memory access indication and early path indication. tolud can be 1 mb aligned. tseg_base the ?tseg_base? register reflects the total amount of low addressable dram, below tolud. bios will calculate and program this register; so, the system agent has knowledge of where (tolud) ? (gfx stolen) ? (gfx gtt stolen) ? (tseg) is located. i/o blocks use this minus dpr for upstream dram decode. 2.3.4.1 memory re-claim background the following are examples of memory mappe d i/o devices are typically located below 4 gb: ?high bios ?tseg ?gfx stolen ?gtt stolen ?xapic ?local apic ? msi interrupts ?mbase/mlimit ? pmbase/pmlimit ? memory mapped io space that supports only 32b addressing the processor provides the capability to re-claim the physical memory overlapped by the memory mapped io logical address spac e. the mch re-maps physical memory from the top of low memory (tolud) boundary up to the 4 gb boundary to an equivalent sized logical address range located just be low the intel management engine stolen memory. datasheet, volume 2 29 processor configuration registers 2.3.4.2 indirect accesses to mchbar registers similar to prior chipsets, mchbar registers can be indirectly accessed using: ? direct mchbar access decode: ? cycle to memory from processor ? hits mchbar base, and ? mchbar is enabled, and ? within mmio space (above and below 4 gb) ? gttmmadr (10000h?13fffh) range -> mchbar decode: ? cycle to memory from processor, and ? device 2 (igd) is enabled, and ? memory accesses for device 2 is enabled, and ? targets graphics mmio function 0, and ? mchbar is enabled or cycle is a read. if mchbar is disabled, only read access is allowed. ?mchtmbar -> mchbar (thermal monitor) ? cycle to memory from processor, and ? and targets mchtmbar base ? iobar -> gttmmadr -> mchbar. ? follows iobar rules. see gttmmadr information above as well. 2.3.4.3 memory remapping an incoming address (referred to as a logical ad dress) is checked to see if it falls in the memory re-map window. the bottom of the re -map window is defined by the value in the remapbase register. the top of the re-map window is defined by the value in the remaplimit register. an address that falls within this window is remapped to the physical memory starting at the address defined by the tolud register. the tolud register must be 1m aligned. 2.3.4.4 hardware remap algorithm the following pseudo-code defines the algorith m used to calculate the dram address to be used for a logical address above the top of physical memory made available using re-claiming. if (address_in[38:20] remap_base[35:20]) and (address_in[38:20] remap_limit[35:20]) then address_out[38:20] = (address_in[38:20] ? remap_base[35:20]) + 0000000b & tolud[31:20] address_out[19:0] = address_in[19:0] processor configuration registers 30 datasheet, volume 2 2.3.4.5 programming model the memory boundaries of interest are: ? bottom of logical address remap window defined by the remapbase register, which is calculated and loaded by bios. ? top of logical address remap window defined by the remaplimit register, which is calculated and loaded by bios. ? bottom of physical remap memory defined by the existing tolud register. ? top of physical remap memory, which is im plicitly defined by either 4 gb or tom minus intel management engine stolen size. mapping steps: 1. determine tom 2. determine tom minus intel me stolen size 3. determine mmio allocation 4. determine tolud 5. determine graphics stolen base 6. determine graphics gtt stolen base 7. determine tseg base 8. determine remap base/limit 9. determine touud the following diagrams show the three possible general cases of remapping. ? case 1: less than 4 gb of physical memory, no remap ? case 2: greater than 4 gb of physical memory ? case 3: 4 gb or less of physical memory datasheet, volume 2 31 processor configuration registers 2.3.4.5.1 case 1 ? less than 4 gb of physical memory (no remap) ? populated physical memory = 2 gb ? address space allocated to memory mapped io = 1 gb ? remapped physical memory = 0 gb ? tom ? 00_7ff0_0000h (2 gb) ? me base ? 00_7ff0_0000h (1 mb) ? me mask ? 00_7ff0_0000h ? touud ? 00_0000_0000h (disable ? avoid access above 4 gb) ? tolud ? 00_7fe0_0000h (2 gb minus 1 mb) ? remapbase ? 7f_ffff_0000h (default) ? remaplimit ? 00_0000_0000h (0 gb boundary, default) figure 2-5. case 1 ? less than 4 gb of physical memory (no remap) ?low dram? os visible < 4 gb pci mmio host/system view physical memory (dram controller view) tseg 0 0 tseg base gfx stolen me-uma tom gfx gtt stolen base me base 1 mb aligned 1 mb aligned 1 mb aligned wasted (only if 4 gb minus pci mmio space is greater than 4 gb minus me stolen base) 1 mb aligned 1 mb aligned 4 gb tolud base 1 mb aligned touud base 1 mb aligned gfx gtt stolen gfx stolen base 1 mb aligned tseg processor configuration registers 32 datasheet, volume 2 2.3.4.5.2 case 2 ? greater than 4 gb of physical memory in this case the amount of memory rema pped is the range between tolud and 4 gb. this physical memory will be mapped to the logical address range defined between the remapbase and the remaplimit registers. figure 2-6. case 2 ? greater than 4 gb of physical memory main memory add range os visible < 4gb pci memory add. range (subtractively decoded to dmi) host/system view physical memory (dram controller view) tseg 0 0 tseg base gfx stolen (0-256 mb) me-uma tom gfx gtt stolen base meseg base 1 mb aligned 1 mb aligned os invisible reclaim 1 mb aligned for reclaim 1 mb aligned 4 gb fec0_0000 1 mb aligned touud base 1 mb aligned gfx gtt stolen (0-2 mb) gfx stolen base 1 mb aligned tseg (0-8 mb) legacy add. range 1 mb main memory address range os visible > 4 gb main memory reclaim add range reclaim base reclaim limit = reclaim base + x 1 mb aligned high pci memory add. range (subtractively decoded to dmi) 1 mb aligned 512 gb x flash, apic intel ? txt (20 mb) tolud base datasheet, volume 2 33 processor configuration registers example: 5 gb of physical memory, with 1 gb allocated to memory mapped io ? populated physical memory = 5 gb ? address space allocated to memory mapped io (including flash, apic, and intel txt) = 1 gb ? remapped physical memory = 1 gb ? tom ? 01_4000_0000h (5 gb) ? me stolen size ? 00000b (0 mb) ? touud ? 01_8000_0000h (6 gb) (1 mb aligned) ? tolud ? 00_c000_000h (3 gb) ? remapbase ? 01_4000_0000h (5 gb) ? remaplimit ? 01_7ff0_0000h (6 gb?1) the remap window is inclusive of the base and limit addresses. in the decoder a[19:0] of the remap base address are assu med to be 0s. similarly, a[19:0] of the remap limit address are assumed to be fs. thus, the bottom of the defined memory range will be aligned to a mb boundary and th e top of the defined range will be one less than a mb boundary. setting the remap base register to a value greater than that programmed into the remap limit register disables the remap function. software responsib ility and restrictions ? bios is responsible for programming the remapbase and remaplimit registers based on the values in the tolud, tom, and intel me stolen size registers. ? the amount of remapped memory defi ned by the remapbase and remaplimit registers must be equal to the amount of physical memory between the tolud and the lower of either 4 gb or tom minus the intel me stolen size. ? addresses of mmio region must not overlap with any part of the logical address memory remap range. ? when tom is equal to tolud, remap is not needed and must be disabled by programming remapbase to a value greate r than the value in the remaplimit register. interaction with other overlapping address space the following memory mapped io address spac es are all logically addressed below 4 gb where they do not overlap the logical a ddress of the re-mapped memory region: gfxgttstolen at (tolud ? gfxstolensize) to tolud gfxstolen at ((tolud ? gfxstolensize) ? gfxgttstolensize) to (tolud ? gfxstolensize) tseg at ((tolud ? gfxstolensize ? gfxgttstolensize) ? tsegsize) to (tolud ? gfxgttstolensize ? gfxstolensize) high bios reset vector just under 4 gb boundary (positive decode to dmi occurs) xapic at fixed address below 4 gb local apic at fixed address below 4 gb processor configuration registers 34 datasheet, volume 2 msi interrupts at fixed address below 4 gb gmadr 64 bit bars gttmmadr 64 bit bars mbase/mlimit pxpepbar 39 bit bar dmibar 39 bit bar mchbar 39 bit bar tmbar 64 bit bar pmbase/pmlimit 64 bit bar (using upper pmbase/pmlimit) chapadr 64 bit bar gfxvtbar 39 bit bars vtdpvc0bar 39 bit bars implementation notes ? remap applies to transactions from all interfaces. all upstream peg/dmi transactions that are snooped get remapped. ? upstream peg/dmi transactions that are not snooped (?snoop not required? attribute set) get remapped. ? upstream reads and writes above to uud are treated as invalid cycles. ? remapped addresses remap starting at tolud. they do not remap starting at tseg_base. dmi and peg need to be careful with this for both snoop and non- snoop accesses. in other words, for upstream accesses, the range between (tolud ? gfxstolensize ? gfxgttstolensize ? tsegsize-dpr) to tolud) will never map directly to memory. note: accesses from peg/dmi should be decoded as to the type of a ccess before they are remapped. for instance, a dmi write to feex_xxxxh is an interrupt transaction, but there is a dmi address that will be re-mappe d to the dram address of feex_xxxxh. in all cases, the remapping of the address is done only after all other decodes have taken place. unmapped addresses between tolud and 4 gb accesses that don?t hit dram or pci space are subtractive decoded to dmi. because the tolud register is used to mark the upper limit of dram space below the 4 gb boundary, no address between tolud and 4 gb ever decodes directly to main memory. thus, even if remap is disabled, any address in this range has a non-memory destination. the top of dram address space is either: ? tolud if there is less than 4 gb of dram or 32-bit addressing or ? touud if there is more than 4 gb of dram and 36-bit addressing note: the system address space includes the remapped range. for instance, if there is 8 gb of dram and 1 gb of pci space, the syst em has a 9 gb address space, where dram lies from 0?3 gb and 4?9 gb. bios will report an address space of 9 gb to the operating system. datasheet, volume 2 35 processor configuration registers 2.3.5 pci express* conf iguration address space pciexbar is located in device 0 configur ation space. the processor detects memory accesses targeting pciexbar. bios must assign this address range such that it will not conflict with any other address ranges. see the configuration portion of this document for more details. 2.3.6 pci express* graphics attach (peg) the processor can be programmed to di rect memory accesses to a pci express interface. when addresses are within either of two ranges specified using registers in each peg(s) configuration space. ? the first range is controlled using the memory base (mbase) register and memory limit (mlimit) register. ? the second range is controlled using the pre-fetchable memory base (pmbase) register and pre-fetchable memory limit (pmlimit) register. conceptually, address decoding for each range follows the same basic concept. the top 12 bits of the respective memory base and memory limit registers correspond to address bits a[31:20] of a memory address. for the purpose of address decoding, the processor assumes that address bits a[19:0] of the memory base are zero and that address bits a[19:0] of the memory limit address are f_ffffh. this forces each memory address range to be aligned to 1 mb boundary and to have a size granularity of 1 mb. the processor positively decodes memory accesses to pci express memory address space as defined by the following equations: memory_base_address address memory_limit_address prefetchable_memory_base_address address prefetchable_memory_limit_address the window size is programmed by the pl ug-and-play configuration software. the window size depends on the size of memory claimed by the pci express device. normally, these ranges will reside above th e top-of-low usable-dram and below high bios and apic address rang es. they must reside above the top of low memory (tolud) if they reside below 4 gb and must reside above top of upper memory (touud) if they reside above 4 gb or they will steal physical dram memory space. it is essential to support a separate pre-fetchable range in order to apply uswc attribute (from the processor point of view) to that range. the uswc attribute is used by the processor for write combining. note: the processor memory range registers described above are used to allocate memory address space for any pci express devices sitting on pci express that require such a window. the pcicmd register can override the routin g of memory accesses to pci express. in other words, the memory access enable bi t must be set to enable the memory base/limit and pre-fetchable base/limit windows. the upper pmubase/pmulimit registers are im plemented for pci express specification compliance. the processor locates mmio space above 4 gb using these registers. processor configuration registers 36 datasheet, volume 2 2.3.7 graphics memo ry address ranges the integrated memory controller can be pr ogrammed to direct memory accesses to igd when addresses are within any of two ranges specified using registers in mch device 2 configuration space. 1. the graphics memory aperture base register (gmadr) is used to access graphics memory allocated using the graphics translation table. 2. the graphics translation table base register (gttadr) is used to access the translation table and graphics control registers. this is part of gttmmadr register. these ranges can reside above the top-of-low-dram and below high bios and apic address ranges. they must reside above th e top of memory (tolud) and below 4 gb so they do not steal any physical dram memory space. alternatively, these ranges can reside above 4 gb, similar to other bars which are larger than 32 bits in size. gmadr is a prefetchable range in order to apply uswc attribute (from the processor point of view) to that range. the uswc a ttribute is used by the processor for write combining. 2.3.7.1 iobar mapped access to device 2 mmio space device 2, integrated graphics device, contains an iobar register. if device 2 is enabled, then igd registers or the gtt ta ble can be accessed using this iobar. the iobar is composed of an index register and a data register. mmio_index : mmio_index is a 32 bit register. a 32-bit (all bytes enabled) i/o write to this port loads the offset of the mmio regi ster or offset into the gtt that needs to be accessed. an i/o read returns the current value of this register. i/o read/write accesses less than 32 bits in size (all bytes enabled) will not target this register. mmio_data : mmio_data is a 32 bit register. a 32 bit (all bytes enabled) i/o write to this port is re-directed to the mmio regist er pointed to by the mmio-index register. an i/o read to this port is re-directed to the mmio register pointed to by the mmio-index register. i/o read/write accesses less than 32 bits in size (all bytes enabled) will not target this register. the result of accesses through iobar can be: ? accesses directed to the gtt table (that is, route to dram). ? accesses to internal graphics registers with the device. ? accesses to internal graphics display registers now located within the pch (that is, route to dmi). note: gtt table space writes (gttadr) are supported through this mapping mechanism. this mechanism to access internal graphics mmio registers must not be used to access vga i/o registers that are mapped through the mmio space. vga registers must be accessed directly through the dedicated vga i/o ports. 2.3.7.2 trusted graphics ranges no trusted graphics ranges are supported. datasheet, volume 2 37 processor configuration registers 2.3.8 system management mode (smm) the core handles all smm mode transaction routing. also, the platform no longer supports hseg. the processor will not allow i/o devices access to cseg/tseg/hseg ranges. dmi interface and pci express* masters are not allowed to access the smm space. 2.3.9 smm and vga access through gtt tlb accesses through gtt tlb address translat ion smm dram space are not allowed. writes will be routed to memory address 000c_0000h with byte enables de-asserted and reads will be routed to memory address 000c_0000h. if a gtt tlb translated address hits smm dram space, the graphics device will report a page table error. pci express* and dmi interface originated accesses are never allowed to access smm space directly or through the gtt tlb addr ess translation. if a gtt tlb translated address hits enabled smm dram space, the graphics device will report a page table error. pci express* and dmi interface write a ccesses through gmadr range will not be snooped. only pci express* and dmi assesse s to gmadr linear range (defined using fence registers) are supported. pci express and dmi interface tiley and tilex writes to gmadr are not supported. if, when translated, the resulting physical address is to enable smm dram space, the request will be remapped to address 000c_0000h with de-asserted byte enables. pci express and dmi interface read accesse s to the gmadr range are not supported; therefore, will have no address translatio n concerns. pci express and dmi interface reads to gmadr will be remapped to addre ss 000c_0000h. the read will complete with ur (unsupported request) completion status. gtt fetches are always decoded (at fetch time) to ensure not in smm (actually, anything above base of tseg or 640 kb?1 mb). thus, they will be invalid and go to address 000c_0000h, but that is not specific to pci express or dmi; it applies to processor or internal graphics engines. 2.3.10 me stolen memory accesses there are only 2 ways to legally access intel me stolen memory: ? pch accesses mapped to vcm will be deco ded to ensure only intel me stolen memory is targeted. these vcm accesses w ill route non-snooped directly to dram. this is the means by which the intel meengi ne (located within the pch) is able to access the intel me stolen range. ? the display engine is allowed to access intel me stolen memory as part of kvm flows. specifically, display initiated hhp reads (for displaying a kvm frame) and display initiated lp non-snoop writes (for display writing a kvm captured frame) to intel me stolen memory are allowed. table 2-4. smm regions smm space enabled transaction address space dram space (dram) compatible 000a_0000h to 000b _ffffh 000a_0000h to 000b_ffffh tseg (tolud ? stolen ? tseg) to tolud ?stolen (tolud ? stolen ? tseg) to tolud ? stolen processor configuration registers 38 datasheet, volume 2 2.3.11 i/o address space the system agent generates either dmi interface or pci express* bus cycles for all processor i/o accesses that it does not claim. configuration address register (config_address) and the configuration data register (config_data) are used to generate pci configuration space access. the processor allows 64k+3 bytes to be addressed within the i/o space. the upper 3 locations can be accessed only during i/o address wrap-around when address bit 16 is asserted. address bit 16 is asserted on the processor bus whenever an i/o access is made to 4 bytes from address 0fffdh, 0fffe h, or 0ffffh. address bit 16 is also asserted when an i/o access is made to 2 bytes from address 0ffffh. a set of i/o accesses are consumed by the internal graphics device if it is enabled. the mechanisms for internal graphics i/o decode and the associated control is explained later. the i/o accesses are forwarded normally to the dmi interface bus unless they fall within the pci express i/o address range as defined by the mechanisms explained below. i/o writes are not posted. memory writes to pch or pci express are posted. the pci express devices have a register that can disable the routing of i/o cycles to the pci express device. the processor responds to i/o cycles initiated on pci express or dmi with an ur status. upstream i/o cycles and configuration cycles should never occur. if one does occur, the transaction will complete with an ur completion status. i/o reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the processor as 1 transaction. it will be divided into 2 separate transactions. i/o writes that lie within 8-byte boundaries but cro ss 4-byte boundaries will be split into 2 transactions by the processor. 2.3.11.1 pci express* i/o address mapping the processor can be programmed to direct non-memory (i/o) accesses to the pci express bus interface when processor initia ted i/o cycle addresses are within the pci express i/o address range. this range is controlled using the i/o base address (iobase) and i/o limit address (iolimit) registers in device 1 functions 0, 1, 2 or device 6 configuration space. address decoding for this range is based on the following concept. the top 4 bits of the respective i/o base and i/o limit registers correspond to address bits a[15:12] of an i/o address. for the purpose of address decoding, the device assumes that lower 12 address bits a[11:0] of the i/o base are zero and that address bits a[11:0] of the i/o limit address are fffh. this forces the i/o address range alignment to 4 kb boundary and produces a size granularity of 4 kb. the processor positively decodes i/o accesses to pci express* i/o address space as defined by the following equation: i/o_base_address processor i/o cycle address i/o_limit_address the effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of i/o space claimed by the pci express device. datasheet, volume 2 39 processor configuration registers the processor also forwards accesses to the legacy vga i/o ranges according to the settings in the peg configuration register s bctrl (vga enable) and pcicmd (ioae), unless a second adapter (monochrome) is present on the dmi interface/pci (or isa). the presence of a second graphics adapter is determined by the mdap configuration bit. when mdap is set, the processor will decode legacy monochrome i/o ranges and forward them to the dmi interface. the i/o ranges decoded for the monochrome adapter are 3b4h, 3b5h, 3b 8h, 3b9h, 3bah, and 3bfh. note: the peg i/o address range registers defined above are used for all i/o space allocation for any devices requiring such a window on pci express*. the pcicmd register can disable the ro uting of i/o cycles to pci express*. 2.3.12 mctp and kvm flows refer to the dmi2 specification for details. mctp cycles are not processed within the processor. mctp cycles are merely passed from input port to destination port based on routing id. 2.3.13 decode rules and cros s-bridge address mapping 2.3.13.1 dmi interface decode rules all ?snoop semantic? pci expr ess* transactions are kept coherent with processor caches. all ?snoop not required semantic? cycles must reference the main dram address range. pci express non-snoop initiated cycles are not snooped. the processor accepts accesses from dmi interface to the following address ranges: ? all snoop memory read and write accesse s to main dram including pam region (except stolen memory ranges, tseg, a0000h?bffffh space) ? write accesses to enabled vga range, mbase/mlimit, and pmbase/pmlimit will be routed as peer cycles to the pci express interface. ? write accesses above the top of usable dr am and below 4 gb (not decoding to pci express or gmadr space) will be treated as master aborts. ? read accesses above the top of usable dram and below 4 gb (not decoding to pci express*) will be treated as unsupported requests. ? reads and accesses above the touud will be treated as unsupported requests on vc0/vcp. dmi interface memory read accesses that fa ll between tolud and 4 gb are considered invalid and will master abort. these invalid read accesses will be reassigned to address 000c_0000h and dispatch to dram. reads will return unsupported request completion. writes targeting pci express space will be treated as peer-to-peer cycles. there is a known usage model for peer writes from dmi to peg. a video capture card can be plugged into the pch pci bus. the video capture card can send video capture data (writes) directly into the frame buffer on an external graphics card (writes to the peg port). as a result, peer writes from dmi to peg must be supported. i/o cycles and configuration cycles are not supported in the upstream direction. the result will be an unsupported request completion status. processor configuration registers 40 datasheet, volume 2 dmi interface accesses to the processor that cross device boundaries the processor does not support transactions that cross device boundaries. this should never occur because pci express transactions are not allowed to cross a 4 kb boundary. for reads, the processor will prov ide separate completion status for each naturally-aligned 64 byte block or, if chaining is enabled, each 128 byte block. if the starting address of a transaction hits a valid address, the portion of a request that hits that target device (pci express or dram) will complete normally. if the starting transaction address hits an invalid address, the entire transaction will be remapped to address 000c_0000h and dispatched to dram. a single unsupported request completion will result. 2.3.13.1.1 tc/vc mapping details 1. vc0 (enabled by default) a. snoop port and non-snoop asynchronous transactions are supported. b. internal graphics gmadr writes ca n occur. these will not be snooped regardless of the snoop not required (snr) bit. c. internal graphics gmadr reads (unsupported). d. peer writes can occur. the snr bit is ignored. e. msi can occur. these will route and be sent to the cores as intlogical/intphysical interrupts regardless of the snr bit. f. vlw messages can occur. these will route and be sent to the cores as vlw messages regardless of the snr bit. g. mctp messages can occur. these are routed in a peer fashion. 2. vcp (optionally enabled) a. supports priority snoop traffic only. this vc is given higher priority at the snoop vc arbiter. routed as an independent virtual channel and treated independently within the cache module. vcp snoops are indicated as ?high priority? in the snoop priority field. usb classic and us b2 traffic are expected to use this channel. note: on prior chipsets, this was termed ?snoop isochronous? traffic. ?snoop isochronous? is now termed ?priority snoop? traffic. b. snr bit is ignored. c. msi on vcp is supported. d. peer read and write requests are not supported. writes will route to address 000c_0000h with byte enables deasserted, while reads will route to address 000c_0000h and an unsupported request completion. e. internal graphics gmadr writes are not supported. these will route to address 000c_0000h with byte enables de-asserted. f. internal graphics gmadr reads are not supported. g. see dmi2 tc mapping for expected tc to vcp mapping. this has changed from dmi to dmi2. 3. vc1 (optionally enabled) a. supports non-snoop transactions only. (used for isochronous traffic). the pci express* egress port (pxpepbar) must also be programmed appropriately. b. the snoop not required (snr) bit must be set. any transaction with the snr bit not set will be treated as an unsupported request. c. msi and peer transactions will be treated as unsupported requests. d. no ?pacer? arbitration or twrr arbitration will occur. never remaps to a different port. (pch takes care of egress port remapping). the pch will meter tcm intel me accesses and intel high definition audio tc1 access bandwidth. datasheet, volume 2 41 processor configuration registers e. internal graphics gmadr writes and gmadr reads are not supported. 4. vcm accesses a. see dmi2 specification for tc mapping to vcm. vcm access only map to intel me stolen dram. these transactions carry the direct physical dram address (no redirection or remapping of any kind will occur). this is how the pch intel management engine accesses its dedicated dram stolen space. b. dmi block will decode these transactions to ensure only intel me stolen memory is targeted, and abort otherwise. c. vcm transactions will only route non-snoop. d. vcm transactions will not go through vtd remap tables. e. the remapbase/remaplimit registers to not apply to vcm transactions. figure 2-7. example: dmi upstream vc0 memory map a0000h?bffffh (vga) gmadr fee0_0000h ? feef_ffffh( msi) tseg_base mem writes ? non-snoop mem write mem reads ? invalid transaction mem writes ? cpu (intlogical/intphysical) mem reads ? invalid transaction mem writes ? peer write (if matching peg range else invalid) mem reads ? invalid transaction 64 gb remaplimit tolud 4 gb remapbase mem writes ? route based on snr bit. mem reads ? route based on snr bit. tom = total physical dram tolud ? (gfx stolen) ? (gfx gtt stolen) (tseg) tseg_base ? dpr 2 tb mem writes ? peer write (based on dev1 vga en) else invalid mem reads ? invalid transaction touud processor configuration registers 42 datasheet, volume 2 2.3.13.2 pci express* interface decode rules all ?snoop semantic? pci express transactions are kept coherent with processor caches. all ?snoop not required semantic? cycles must reference the direct dram address range. pci express* non-snoop initiated cycles are not snooped. if a ?snoop not required semantic? cycle is outside of the address range mapped to system memory, then it will proceed as follows: ? reads: sent to dram address 000c_0000h (non-snooped) and will return ?unsuccessful completion?. ? writes: sent to dram address 000c_0000h (non-snooped) with byte enables all disabled peer writes from peg to dmi are not supported. if peg bus master enable is not set, all reads and writes are treated as unsupported requests. 2.3.13.2.1 tc/vc mapping details 1. vc0 (enabled by default) a. snoop port and non-snoop asynchronous transactions are supported. b. internal graphics gmadr writes ca n occur. these will not be snooped regardless of the snoop not required (snr) bit. c. internal graphics gmadr reads (unsupported). d. peer writes are only supported betw een peg ports. peg to dmi peer write accesses are not supported. e. msi can occur. these will route to the cores (intlogical/intphysical) regardless of the snr bit. 2. vc1 is not supported 3. vcm is not supported datasheet, volume 2 43 processor configuration registers 2.3.13.3 legacy vga and i/o range decode rules the legacy 128 kb vga memory range 000a_0000h?000b_ffffh can be mapped to igd (device 2), pci express (device 1 functions or device 6), and/or to the dmi interface depending on the programming of the vga steering bits. priority for vga mapping is constant in that the processor always decodes internally mapped devices first. internal to the processor, decode precedence is always given to igd. the processor always positively decodes internally mapped devices, namely the igd. subsequent decoding of regions mapped to either pci express port or the dmi interface depends on the legacy vga conf igurations bits (vga enable & mdap). for the remainder of this sect ion, pci express can refer to either the device 1 port functions or the device 6 port. vga range accesses will always be mapped as uc type memory. figure 2-8. peg upstream vc0 memory map a0000h?bffffh (vga) gmadr fee0_0000h ? feef_ffffh( msi) tseg_base mem writes ? non-snoop mem write mem reads ? invalid transaction mem writes ? cpu (intlogical/intphysical) mem reads ? invalid transaction mem writes ? peer write (if matching peg range else invalid) mem reads ? invalid transaction 64 gb remaplimit tolud 4 gb remapbase mem writes ? route based on snr bit. mem reads ? route based on snr bit. tom = total physical dram upstream initiated vc0 cycle memory map tolud ? (gfx stolen) ? (gfx gtt stolen) (tseg) tseg_base ? dpr 2 tb mem writes ? invalid transaction mem reads ? invalid transaction touud processor configuration registers 44 datasheet, volume 2 accesses to the vga memory range are directed to igd depend on the configuration. the configuration is specified by: ? internal graphics controller in device 2 is enabled (deven.d2en bit 4) ? internal graphics vga in device 0 function 0 is enabled through register ggc bit 1. ? igd memory accesses (pcicmd2 04 ? 05h, mae bit 1) in device 2 configuration space are enabled. ? vga compatibility memory accesses (vga miscellaneous output register ? msr register, bit 1) are enabled. ? software sets the proper value for vga memory map mode register (vga gr06 register, bits 3:2). see ta b l e 2 - 5 for translations. note: additional qualification within igd compre hends internal mda support. the vga and mda enabling bits detailed below control segments not mapped to igd. vga i/o range is defined as addresses where a[15:0] are in the ranges 03b0h to 03bbh, and 03c0h to 03dfh. vga i/o acce sses directed to igd depends on the following configuration: ? internal graphics controller in device 2 is enabled through register deven.d2en bit 4. ? internal graphics vga in device 0 function 0 is enabled through register ggc bit 1. ? igd i/o accesses (pcicmd2 04 ? 05h, ioae bit 0) in device 2 are enabled. ? vga i/o decodes for igd uses 16 address bits (15:0) there is no aliasing. this is different when compared to a bridge device (device 1) that used only 10 address bits (a 9:0) for vga i/o decode. ? vga i/o input/output address select (v ga miscellaneous output register ? msr register, bit 0) used to select mapping of i/o access as defined in table 2-6 . note: additional qualification within igd compre hends internal mda support. the vga and mda enabling bits detailed below control ranges not mapped to igd. table 2-5. igd frame buffer accesses mem access ? gr06(3:2) a0000h?affffh b0000h?b7fffh mda b8000h?bffffh 00 igd igd igd 01 igd pci express bridge or dmi interface pci express bridge or dmi interface 10 pci express bridge or dmi interface igd pci express bridge or dmi interface 11 pci express bridge or dmi interface pci express bridge or dmi interface igd table 2-6. igd vga i/o mapping i/o access ? msrb0 3cxh 3dxh 3b0h?3bbh 3bch?3bfh 0igd pci express bridge or dmi interface igd pci express bridge or dmi interface 1igd igd pci express bridge or dmi interface pci express bridge or dmi interface datasheet, volume 2 45 processor configuration registers for regions mapped outside of the igd (or if igd is disabled), the legacy vga memory range a0000h?bffffh are mapped either to the dmi interface or pci express depending on the programming of the vga enable bit in the bctrl configuration register in the peg configuration space, and the mdapxx bits in the legacy access control (lac) register in device 0 configuration space. the same register controls mapping vga i/o address ranges. vga i/o range is defined as addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases ? a[15:10] are not decoded). the function and interaction of these two bits is described below: vga enable: controls the routing of processor initiated transactions targeting vga compatible i/o and memory address ranges . when this bit is set, the following processor accesses will be forwarded to the pci express*: ? memory accesses in the range 0a0000h to 0bffffh ? i/o addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (including isa address aliases ? a[15:10] are not decoded) when this bit is set to a ?1?: ? forwarding of these accesses issued by the processor is independent of the i/o address and memory address ranges define d by the previously defined base and limit registers. ? forwarding of these accesses is also independent of the settings of the isa enable settings if this bit is ?1?. ? accesses to i/o address range x3bch?x3 bfh are forwarded to dmi interface. when this bit is set to a ?0?: ? accesses to i/o address range x3bch?x3bfh are treated just like any other i/o accesses ? that is, the cycles are forwarded to pci express if the address is within iobase and iolimit and isa enable bit is not set; otherwise, they are forwarded to dmi interface. ? vga compatible memory and i/o range a ccesses are not forwarded to pci express but rather they are mapped to dmi inte rface unless they are mapped to pci express using i/o and memory range regi sters defined above (iobase, iolimit) table 2-7 shows the behavior for all combinations of mda and vga. the same registers control mapping of vga i/o address ranges. vga i/o range is defined as addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases ? a[15:10] are not decoded). the function and interaction of these two bits is described below. table 2-7. vga and mda i/o transaction mapping vga_en mdap range destination exceptions/notes 0 0 vga, mda dmi interface 0 1 illegal undefined behavior results 10vgapci express 11vgapci express 1 1 mda dmi interface note: x3bch?x3beh will also go to dmi interface processor configuration registers 46 datasheet, volume 2 mda present (mdap): this bit works with the vga enable bit in the bctrl register of device 1 to control the routing of processor initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set when the vga enable bit is not set. if the vga enable bi t is set, accesses to i/o address range x3bch? x3bfh are forwarded to dmi interface. if the vga enable bit is not set, accesses to i/o address range x3bch?x3bfh are treated just like any other i/o accesses ? that is, the cycles are forwarded to pci express if the address is within iobase and iolimit and isa enable bit is not set; otherwise, th ey are forwarded to dmi interface. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes the i/o locati ons listed above, or their aliases, will be forwarded to dmi interface even if the re ference includes i/o locations not listed above. for i/o reads which are split into multiple dw ord accesses, this decode applies to each dword independently. for example, a read to x3b3 and x3b4 (qua dword read to x3b0 with be#=e7h) will result in a dword read from peg at 3b0 (be#=eh), and a dword read from dmi at 3b4 (be=7h ). since the processor will not issue i/o writes crossing the dword boundary, this special case does not exist for writes. summary of decode priority: 1. internal graphics vga, if enabled, gets: 03c0h?03cfh: always 03b0h?03bbh: if msr[0]=0 (msr is i/o register 03c2) 03d0h?03dfh: if msr[0]=1 note: 03bch?03bfh never decodes to igd; 3bch?3beh are parallel port i/os, and 3bf is only used by true mda devices, apparently. 2. else, if mda present (if vga on peg is enabled), dmi gets: x3b4,5,8,9,a,f (any access with any of these bytes enabled, regardless of the other bes) 3. else, if vga on peg is enabled, peg gets: x3b0h?x3bbh x3c0h?x3cfh x3d0h?x3dfh 4. else, if isa enable=1, dmi gets: upper 768 bytes of each 1k block 5. else, iobase/iolimit apply 2.4 i/o mapped registers the processor contains two registers that reside in the processor i/o address space ? the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what po rtion of configuration space is visible through the configuration data window. datasheet, volume 2 47 processor configuration registers 2.5 pci device 0 function 0 configuration space registers table 2-8. pci device 0, func tion 0 configuration space re gister address map (sheet 1 of 2) address offset register symbol register name reset value access 0?1h vid vendor identification 8086h ro 2?3h did device identification 0150h ro-fw, ro-v 4?5h pcicmd pci command 0006h ro, rw 6?7h pcists pci status 0090h rw1c, ro 8h rid revision identification 00h ro-fw 9?bh cc class code 060000h ro c?dh rsvd reserved 0h ro eh hdr header type 00h ro f?2bh rsvd reserved 0h ro 2c?2dh svid subsystem vendor identification 0000h rw-o 2e?2fh sid subsystem identification 0000h rw-o 30?33h rsvd reserved 0h ro 34h capptr capabilities pointer e0h ro 35?3fh rsvd reserved 0h ro 40?47h pxpepbar pci express egress port base address 00000000000 00000h rw 48?4fh mchbar host memory mapped register range base 00000000000 00000h rw 50?51h ggc gmch graphics control register 0028h rw-l, rw-kl 52?53h rsvd reserved 0h ro 54?57h deven device enable 0000209fh rw-l, ro, rw 58?5bh pavpc protected audio video path control 00000000h rw-l, rw-kl 5c?5fh dpr dma protected range 00000000h rw-l, ro-v, rw-kl 60?67h pciexbar pci express register range base address 00000000000 00000h rw, rw-v 68?6fh dmibar root complex register range base address 00000000000 00000h rw 70?77h meseg_base intel management engine base address register 0000007ffff0 0000h rw-l 78?7fh meseg_mask intel management engine limit address register 00000000000 00000h rw-l, rw-kl 80h pam0 programmable attribute map 0 00h rw 81h pam1 programmable attribute map 1 00h rw 82h pam2 programmable attribute map 2 00h rw 83h pam3 programmable attribute map 3 00h rw 84h pam4 programmable attribute map 4 00h rw 85h pam5 programmable attribute map 5 00h rw 86h pam6 programmable attribute map 6 00h rw 87h lac legacy access control 00h rw 88h rsvd reserved 02h rw-lv, rw-l, rw-kl, ro processor configuration registers 48 datasheet, volume 2 2.5.1 vid?vendor identification register this register combined with the device identification register uniquely identifies any pci device. 89?8fh rsvd reserved 0h ro 90?97h remapbase remap base address register 0000000ffff0 0000h rw-l, rw-kl 98?9fh remaplimit remap limit address register 00000000000 00000h rw-l, rw-kl a0?a7h tom top of memory 0000007ffff0 0000h rw-l, rw-kl a8?afh touud top of upper usable dram 00000000000 00000h rw-kl, rw-l b0?b3h bdsm base data of stolen memory 00000000h rw-kl, rw-l b4?b7h bgsm base of gtt stolen memory 00100000h rw-l, rw-kl b8?bbh tsegmb tseg memory base 00000000h rw-l, rw-kl bc?bfh tolud top of low usable dram 00100000h rw-kl, rw-l c0?dbh rsvd reserved 0h ro dc?dfh skpd scratchpad data 00000000h rw e0?e3h rsvd reserved 0h ro e4?e7h capid0_a capabilities a 00000000h ro-fw, ro-kfw e8?ebh capid0_b capabilities b 00000000h ro-fw, ro-kfw c8?c9h errsts error status 0000h rw1cs ca?cbh errcmd error command 0000h rw cc?cdh smicmd smi command 0000h rw ce?cfh scicmd sci command 0000h rw table 2-8. pci device 0, function 0 configur ation space register address map (sheet 2 of 2) address offset register symbol register name reset value access b/d/f/type: 0/0/0/pci address offset: 0?1h reset value: 8086h access: ro size: 16 bits bit access reset value rst/ pwr description 15:0 ro 8086h uncore vendor identification number (vid) pci standard identification for intel. datasheet, volume 2 49 processor configuration registers 2.5.2 did?device identification register this register combined with the vendor identification register uniquely identifies any pci device. 2.5.3 pcicmd?pci command register since device 0 does not physically reside on pci_a many of the bits are not implemented. b/d/f/type: 0/0/0/pci address offset: 2?3h reset value: 0150h access: ro-fw, ro-v size: 16 bits bit access reset value rst/ pwr description 15:4 ro-fw 015h uncore device identification number msb (did_msb) this is the upper part of device identification assigned to the processor. 3:2 ro-v 00b uncore device identification number sku (did_sku) this is the middle pa rt of device identification assigned to the processor. 1:0 ro-fw 00b uncore device identification number lsb (did_lsb) this is the lower part of device identification assigned to the processor. b/d/f/type: 0/0/0/pci address offset: 4?5h reset value: 0006h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:10 ro 0h reserved (rsvd) 9ro 0buncore fast back-to-back enable (fb2b) this bit controls whether or not the master can do fast back-to- back write. since device 0 is st rictly a target this bit is not implemented and is hardwired to 0. writes to this bit position have no effect. 8rw 0buncore serr enable (serre) this bit is a global enable bit for device 0 serr messaging. the processor communicates the serr condition by sending an serr message over dmi to the pch. 1 = the processor is enabled to generate serr messages over dmi for specific device 0 error conditions that are individually enabled in the errcmd and dmiuemsk registers. the error status is reported in the errsts, pcists, and dmiu est registers. 0 = the serr message is not generated by the host for device 0. this bit only controls serr messaging for device 0. other integrated devices have their own serre bits to control error reporting for error conditions occurring in each device. the control bits are used in a logi cal or manner to enable the serr dmi message mechanism. 0 = device 0 serr disabled 1 = device 0 serr enabled processor configuration registers 50 datasheet, volume 2 2.5.4 pcists?pci status register this status register reports the occurrence of error events on device 0's pci interface. since device 0 does not physically reside on pci_a many of the bits are not implemented. 7 ro 0b uncore address/data stepping enable (adstep) address/data stepping is not implemented in the processor, and this bit is hardwired to 0. writes to this bit position have no effect. 6 rw 0b uncore parity error enable (perre) this bit controls whether or not the master data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register can not be set. 1 = master data parity error bit in pci status register can be set. 5 ro 0b uncore vga palette snoop enable (vgasnoop) the processor does not implement this bit and it is hardwired to a 0. writes to this bit position have no effect. 4 ro 0b uncore memory write and invalidate enable (mwie) the processor will never issu e memory write and invalidate commands. this bit is therefore hardwired to 0. writes to this bit position will have no effect. 3ro 0h reserved (rsvd) 2 ro 1b uncore bus master enable (bme) the processor is always enabled as a master on the backbone. this bit is hardwired to a 1. writes to this bit position have no effect. 1 ro 1b uncore memory access enable (mae) the processor always allows access to main memory, except when such access would violate security principles. such exceptions are outside the scope of pci control. this bit is not implemented and is hardwired to 1. writes to this bit position have no effect. 0 ro 0b uncore i/o access enable (ioae) this bit is not implemented in the processor and is hardwired to a 0. writes to this bit position have no effect. b/d/f/type: 0/0/0/pci address offset: 4?5h reset value: 0006h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/pci address offset: 6?7h reset value: 0090h access: rw1c, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15 rw1c 0b uncore detected parity error (dpe) this bit is set when this de vice receives a poisoned tlp. datasheet, volume 2 51 processor configuration registers 14 rw1c 0b uncore signaled system error (sse) this bit is set to 1 when device 0 generates an serr message over dmi for any enabled device 0 error condition. device 0 error conditions are enabled in the pcicmd, errcmd, and dmiuemsk registers. device 0 error flags are read/reset from the pcists, errsts, or dmiuest registers. software clears this bit by writing a 1 to it. 13 rw1c 0b uncore received master abort status (rmas) this bit is set when the proces sor generates a dmi request that receives an unsupported request completion packet. software clears this bit by writing a 1 to it. 12 rw1c 0b uncore received target abort status (rtas) this bit is set when the proces sor generates a dmi request that receives a completer abort completion packet. software clears this bit by writing a 1 to it. 11 ro 0b uncore signaled target abort status (stas) the processor will not generate a target abort dmi completion packet or special cycle. this bit is not implemented and is hardwired to a 0. writes to this bit position have no effect. 10:9 ro 00b uncore devsel timing (devt) these bits are hardwired to 00. writes to these bit positions have no effect. device 0 does not phys ically connect to pci_a. these bits are set to 00 (fast decode) so that optimum devsel timing for pci_a is not limited by the host. 8 rw1c 0b uncore master data parity error detected (dpd) this bit is set when dmi received a poisoned completion from pch. this bit can only be set when the parity error enable bit in the pci command register is set. 7 ro 1b uncore fast back-to-back (fb2b) this bit is hardwired to 1. writes to these bit positions have no effect. device 0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for pci_a is not limited by the host. 6ro 0h reserved (rsvd) 5 ro 0b uncore 66 mhz capable (mc66) does not apply to pci express. must be hardwired to 0. 4 ro 1b uncore capability list (clist) this bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed using register capptr at configuration address offset 34h. register capptr contains an offset pointing to the start addr ess within configuration space of this device where the capability identification register resides. 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/pci address offset: 6?7h reset value: 0090h access: rw1c, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 52 datasheet, volume 2 2.5.5 rid?revision identification register this register contains the revision number of device 0. these bits are read only and writes to this register have no effect. 2.5.6 cc?class code register this register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. b/d/f/type: 0/0/0/pci address offset: 8h reset value: 00h access: ro-fw size: 8 bits bit access reset value rst/ pwr description 7:0 ro-fw 0h uncore revision identification number (rid) refer to the intel ? xeon ? processor e3-1200 v2 product family specification update for the value of the rid register. b/d/f/type: 0/0/0/pci address offset: 9?bh reset value: 060000h access: ro size: 24 bits bit access reset value rst/ pwr description 23:16 ro 06h uncore base class code (bcc) this is an 8-bit value that indicates the base class code for the host bridge device. this code has the value 06h, indicating a bridge device. 15:8 ro 00h uncore sub-class code (subcc) this is an 8-bit value that indica tes the category of bridge into which the host bridge device falls . the code is 00h indicating a host bridge. 7:0 ro 00h uncore programming interface (pi) this is an 8-bit value that indi cates the programming interface of this device. this value does not specify a particular register set layout and provides no practical use for this device. datasheet, volume 2 53 processor configuration registers 2.5.7 hdr?header type register this register identifies the header layout of the configuration space. no physical register exists at this location. 2.5.8 svid?subsystem vendor identification register this value is used to identify the vendor of the subsystem. 2.5.9 sid?subsystem identification register this value is used to identify a particular subsystem. b/d/f/type: 0/0/0/pci address offset: eh reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore pci header (hdr) this field always returns 0 to indicate that the host bridge is a single function device with standard header layout. reads and writes to this location have no effect. b/d/f/type: 0/0/0/pci address offset: 2c?2dh reset value: 0000h access: rw-o size: 16 bits bit access reset value rst/ pwr description 15:0 rw-o 0000h uncore subsystem vendor id (subvid) this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. b/d/f/type: 0/0/0/pci address offset: 2e?2fh reset value: 0000h access: rw-o size: 16 bits bit access reset value rst/ pwr description 15:0 rw-o 0000h uncore subsystem id (subid) this field should be programmed during bios initialization. after it has been written once, it becomes read only. processor configuration registers 54 datasheet, volume 2 2.5.10 capptr?capabilities pointer register the capptr provides the offset that is the pointer to the location of the first device capability in the capability list. 2.5.11 pxpepbar?pci express* egress port base address register this is the base address for the pci expre ss* egress port mmio configuration space. there is no physical memory within this 4 kb window that can be addressed. the 4 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, the egress port mmio configuration space is disabled and must be enabled by writing a 1 to pxpepbaren [device 0, offset 40h, bit 0]. all the bits in this register are locked in intel txt mode. b/d/f/type: 0/0/0/pci address offset: 34h reset value: e0h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro e0h uncore capabilities pointer (capptr) pointer to the offset of the first capability id register block. in this case the first capability is the product-specific capability identifier (capid0). b/d/f/type: 0/0/0/pci address offset: 40?47h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore pci express egress port mmio base address (pxpepbar) this field corresponds to bits 38:12 of the base address pci express egress port mmio conf iguration space. bios will program this register resulting in a base address for a 4 kb block of contiguous memory address space. this register ensures that a naturally aligned 4 kb space is allocated within the first 512 gb of addressable memory space. system software uses this base address to program the pci express egress port mmio register set. all the bits in this regist er are locked in intel txt mode. 11:1 ro 0h reserved (rsvd) 0rw 0buncore pxpepbar enable (pxpepbaren): 0 = disable. pxpepbar is disabled and does not claim any memory 1 = enable. pxpepbar memory mapped accesses are claimed and decoded appropriately this register is locked by intel txt. datasheet, volume 2 55 processor configuration registers 2.5.12 mchbar?host memory ma pped register range base register this is the base address for the host memory mapped configuration space. there is no physical memory within this 32 kb window that can be addressed. the 32 kb reserved by this register does not alias to any pc i 2.3 compliant memory mapped space. on reset, the host mmio memory mapped configuration space is disabled and must be enabled by writing a 1 to mchbaren [device 0, offset 48h, bit 0]. all the bits in this register are locked in intel txt mode. the register space contains memory control, initialization, timing , and buffer strength registers; clocking registers; and power and thermal management registers. 2.5.13 ggc?gmch graphics control register all the bits in this register are intel txt lockable. b/d/f/type: 0/0/0/pci address offset: 48?4fh reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 0000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:15 rw 000000h uncore host memory mapped base address (mchbar) this field corresponds to bits 38:15 of the base address host memory mapped configuration sp ace. bios will program this register resulting in a base address for a 32 kb block of contiguous memory address space. this register ensures that a naturally aligned 32 kb space is allocated within the first 512 gb of addressable memory space. system software uses this base address to program the host memory mapped register set. all the bits in this register are locked in intel txt mode. 14:1 ro 0h reserved (rsvd) 0rw 0buncore mchbar enable (mchbaren) 0 = disable. mchbar is disabled and does not claim any memory 1 = enable. mchbar memory mapped accesses are claimed and decoded appropriately this register is locked by intel txt. b/d/f/type: 0/0/0/pci address offset: 50?51h reset value: 0028h access: rw-l, rw-kl size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15 ro 0h reserved (rsvd) 14 rw-l 0b uncore reserved (rsvd) 13:10 ro 0h reserved (rsvd) processor configuration registers 56 datasheet, volume 2 9:8 rw-l 0h uncore gtt graphics memory size (ggms) this field is used to select the amount of main memory that is pre-allocated to support the intern al graphics translation table. the bios ensures that memory is pre-allocated only when internal graphics is enabled. gsm is assumed to be a contiguous physical dram space with dsm, and bios needs to allocate a contiguous memory chunk. hardware will derive the base of gsm from dsm only using the gsm size programmed in the register. hardware functionality in case of programming this value to reserved is not ensured. 0h = no preallocated memory 1h = 1 mb of preallocated memory 2h = 2 mb of preallocated memory 3h = reserved 7:3 rw-l 05h uncore graphics mode select (gms) this field is used to select the amount of main memory that is pre-allocated to support the inte rnal graphics device in vga (non-linear) and native (linear) modes. the bios ensures that memory is pre-allocated only when internal graphics is enabled. this register is also intel txt lockable. hardware does not clear or set any of these bits automatically based on igd being disabled/enabled. bios requirement: bios must not set this field to 0h if ivd (bit 1 of this register) is 0. note: it is recommended that the 1 gb pre-allocated memory option be used for systems with at least 2 gb physical dram. encodings are as follows: 0h = 0 mb 1h = 32 mb 2h = 64 mb 3h = 96 mb 4h = 128 mb 5h = 160 mb 6h = 192 mb 7h = 224 mb 8h = 256 mb 9h = 288 mb ah = 320 mb bh = 352 mb ch = 384 mb dh = 416 mb eh = 448 mb fh = 480 mb 10h = 512 mb 11h = 1 gb other = reserved b/d/f/type: 0/0/0/pci address offset: 50?51h reset value: 0028h access: rw-l, rw-kl size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description datasheet, volume 2 57 processor configuration registers 2.5.14 deven?device enable register this register allows for enabling/disabling of pci devices and functions that are within the processor package. the following table bi t definitions describe the behavior of all combinations of transactions to devices controlled by this register. all the bits in this register are intel txt lockable. 2ro 0h reserved (rsvd) 1rw-l 0b uncore igd vga disable (ivd) 0 = enable. device 2 (igd) claims vga memory and i/o cycles, the sub-class code within device 2 class code register is 00. 1 = disable. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub- class code field within device 2 function 0 class code register is 80. bios requirement: bios must not set this bit to 0 if the gms field (bits 7:3 of this register) pre-allocates no memory. this bit must be set to 1 if device 2 is disabled either using a fuse or fuse override (capid0_a [igd] = 1) or using a register (deven[3] = 0). this register is locked by intel txt lock. 0 = enable 1 = disable 0rw-kl 0b uncore ggc lock (ggclck) when set to 1b, this bit will lo ck all bits in this register. b/d/f/type: 0/0/0/pci address offset: 50?51h reset value: 0028h access: rw-l, rw-kl size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/pci address offset: 54?57h reset value: 0000209fh access: rw-l, ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:15 ro 0h reserved (rsvd) 14 rw 0b uncore chap enable (d7en) 0 = bus 0 device 7 is disabled and not visible. 1 = bus 0 device 7 is enabled and visible. non-production bios code should provide a setup option to enable bus 0 device 7. when enabled, bus 0 device 7 must be initialized in accordance to st andard pci device initialization procedures. 13 rw-l 1b uncore peg60 enable (d6f0en) 0 = bus 0 device 6 function 0 is disabled and hidden. 1 = bus 0 device 6 function 0 is enabled and visible. this bit will be set to 0b and re main 0b if peg60 capability is disabled. 12:8 ro 0h reserved (rsvd) processor configuration registers 58 datasheet, volume 2 7rw-l 1b uncore device 4 enable (d4en) 0 = bus 0 device 4 is disabled and not visible. 1 = bus 0 device 4 is enabled and visible. this bit will be set to 0b and re main 0b if device 4 capability is disabled. 6:5 ro 0h reserved (rsvd) 4rw-l 1b uncore internal graphics engine (d2en) 0 = bus 0 device 2 is disabled and hidden 1 = bus 0 device 2 is enabled and visible this bit will be set to 0b and re main 0b if device 2 capability is disabled. 3rw-l 1b uncore peg10 enable (d1f0en) 0 = bus 0 device 1 function 0 is disabled and hidden. 1 = bus 0 device 1 function 0 is enabled and visible. this bit will be set to 0b and remain 0b if peg10 capability is disabled. 2rw-l 1b uncore peg11 enable (d1f1en) 0 = bus 0 device 1 function 1 is disabled and hidden. 1 = bus 0 device 1 function 1 is enabled and visible. this bit will be set to 0b and remain 0b if: ? peg11 capability is disabled by fuses, or ? peg11 is disabled by strap (peg0cfgsel) 1rw-l 1b uncore peg12 enable (d1f2en) 0 = bus 0 device 1 function 2 is disabled and hidden. 1 = bus 0 device 1 function 2 is enabled and visible. this bit will be set to 0b and remain 0b if: ? peg12 capability is disabled by fuses, or ? peg12 is disabled by strap (peg0cfgsel) 0ro 1buncore host bridge (d0en) bus 0 device 0 function 0 may not be disabled and is therefore hardwired to 1. b/d/f/type: 0/0/0/pci address offset: 54?57h reset value: 0000209fh access: rw-l, ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description datasheet, volume 2 59 processor configuration registers 2.5.15 pavpc?protected audio video path control register all the bits in this register are locked by intel txt. when locked, the rw bits are ro. 2.5.16 dpr?dma protec ted range register dma protected range register. b/d/f/type: 0/0/0/pci address offset: 58?5bh reset value: 00000000h access: rw-l, rw-kl size: 32 bits bit access reset value rst/ pwr description 31:3 ro 0h reserved (rsvd) 2rw-kl 0b uncore pavp lock (pavplck) this bit will lock all writeable cont ents in this re gister when set (including itself). only a hardware reset can unlock the register again. for the processor, this lock bit needs to be set only if pavp is enabled (bit_pavpe = '1`). 1:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/pci address offset: 5c?5fh reset value: 00000000h access: rw-l, ro-v, rw-kl size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31:3 ro 0h reserved (rsvd) 2rw-l 0b uncore enable protected memory (epm) this field controls dma accesses to the dma protected range (dpr) region. 0 = dpr is disabled 1 = dpr is enabled. all dma requ ests accessing dpr region are blocked. hardware reports the status of dpr enable/disable through the prs field in this register. 1ro-v 0b uncore protected region status (prs) this field indicates the status of dpr. 0 = dpr protection disabled 1 = dpr protection enabled 0ro 0h reserved (rsvd) processor configuration registers 60 datasheet, volume 2 2.5.17 pciexbar?pci express* register range base address register this is the base address for the pci expr ess configuration space. this window of addresses contains the 4 kb of configuration space for each pci express device that can potentially be part of the pci express hierarchy associated with the uncore. there is no actual physical memory within this window of up to 256 mb that can be addressed. the actual size of this range is determined by a field in this register. each pci express hierarchy requires a pci express base register. the uncore supports one pci express hierarchy. the region reserved by this register does not alias to any pci2.3 compliant memory mapped space. for example, the range reserved for mchbar is outside of pciexbar space. on reset, this register is disabled and must be enabled by writing a 1 to the enable field in this register. this base address shall be assigned on a boundary consistent with the number of buses (defined by the length field in this register), above tolud and still within 39-bit addressable memory space. the pci express base address cannot be less than the maximum address written to the top of physical memory register (tolud). so ftware must ensure that these ranges do not overlap with known ranges located above tolud. software must ensure that the sum of the le ngth of the enhanced configuration region + tolud + any other known ranges reserved above tolud is not greater than the 39- bit addessable limit of 512 gb. in general, system implementation and the number of pci/pci express/pci-x buses su pported in the hierarchy will dictate the length of the region. all the bits in this register are locked in intel txt mode. b/d/f/type: 0/0/0/pci address offset: 60?67h reset value: 0000000000000000h access: rw, rw-v size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:28 rw 000h uncore pci express* base address (pciexbar) this field corresponds to bits 38:28 of the base address for pci express enhanced configuration space. bios will program this register resulting in a base ad dress for a contiguous memory address space. the size of the range is defined by bits 2:1 of this register. this base address shall be assigned on a boundary consistent with the number of buses (defined by the length field in this register) above tolud and still within the 39-bit addressable memory space. the address bits decoded depend on the length of the region defined by this register. this register is locked by intel txt. the address used to access the pci express configuration space for a specific device can be determined as follows: pci express base address + bus number * 1mb + device number * 32 kb + function number * 4 kb this address is the beginning of the 4 kb space that contains both the pci compatible configuration space and the pci express extended configuration space. datasheet, volume 2 61 processor configuration registers 27 rw-v 0b uncore 128 mb base address mask (admsk128) this bit is either part of the pci express base address (rw) or part of the address mask (ro, read 0b), depending on the value of bits 2:1 in this register. 26 rw-v 0b uncore 64 mb base address mask (admsk64) this bit is either part of the pci express base address (rw) or part of the address mask (ro, read 0b), depending on the value of bits 2:1 in this register. 25:3 ro 0h reserved (rsvd) 2:1 rw 00b uncore length (length) this field describes the length of this region. 00 = 256 mb (buses 0?255). bits 38:28 are decoded in the pci express base address field. 01 = 128 mb (buses 0?127). bits 38:27 are decoded in the pci express base address field. 10 = 64 mb (buses 0?63). bits 38:26 are decoded in the pci express base address field. 11 = reserved. this register is locked by intel txt. 0rw 0buncore pciexbar enable (pciexbaren) 0 = the pciexbar register is disabled. memory read and write transactions proceed as if there were no pciexbar register. pciexbar bits 38:26 are rw with no functionality behind them. 1 = the pciexbar register is enabled. memory read and write transactions whose address bits 38:26 match pciexbar will be translated to configuration reads and writes within the uncore. these translated cycles are routed as shown in the above table. this register is locked by intel txt. b/d/f/type: 0/0/0/pci address offset: 60?67h reset value: 0000000000000000h access: rw, rw-v size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description processor configuration registers 62 datasheet, volume 2 2.5.18 dmibar?root complex re gister range base address register this is the base address for the root comp lex configuration space. this window of addresses contains the root complex register set for the pci express* hierarchy associated with the host bridge. there is no physical memory within this 4 kb window that can be addressed. the 4 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, the root complex configuration space is disabled and must be enabled by writing a 1 to dmibaren [device 0, offset 68h, bit 0]. all the bits in this register are locked in intel txt mode. b/d/f/type: 0/0/0/pci address offset: 68?6fh reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore dmi base address (dmibar) this field corresponds to bits 38:12 of the base address dmi configuration space. bios will prog ram this register resulting in a base address for a 4 kb block of contiguous memory address space. this register ensures that a naturally aligned 4 kb space is allocated within the first 512 gb of addressable memory space. system software uses this base address to program the dmi register set. all the bits in this register are locked in intel txt mode. 11:1 ro 0h reserved (rsvd) 0rw 0buncore dmibar enable (dmibaren) 0 = disable. dmibar is disabled and does not claim any memory 1 = enable. dmibar memory mapped accesses are claimed and decoded appropriately this register is locked by intel txt. datasheet, volume 2 63 processor configuration registers 2.5.19 meseg_base?intel ? management engine base address register this register determines the base address register of the memory range that is pre- allocated to the intel management engine. together with the meseg_mask register it controls the amount of memory allocated to the me. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are a ssumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. this register is locked by intel txt. note: bios must program meseg_base and meseg_mask so that intel me stolen memory is carved out from tom. b/d/f/type: 0/0/0/pci address offset: 70?77h reset value: 0000007ffff00000h access: rw-l size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw-l 7ffffh uncore me uma memory base address (mebase) this field corresponds to a[38:20] of the base address memory range that is allocated to the me. 19:0 ro 0h reserved (rsvd) processor configuration registers 64 datasheet, volume 2 2.5.20 meseg_mask?intel ? management engine limit address register this register determines the mask address register of the memory range that is pre- allocated to the intel management engine. to gether with the mese g_base register it controls the amount of memory allocated to the me. this register is locked by intel txt. note: bios must program meseg_base and meseg_m ask so that intel me stolen memory is carved out from tom. b/d/f/type: 0/0/0/pci address offset: 78?7fh reset value: 0000000000000000h access: rw-l, rw-kl size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw-l 00000h uncore me uma memory mask (memask) this field indicates the bits that must match mebase in order to qualify as an intel mememory range access. for example, if the field is set to 7ffffh, then in tel mememory is 1 mb in size. another example is that if the field is set to 7fffeh, then intel mememory is 2 mb in size. in other words, the size of inte l mememory range is limited to power of 2 times 1 mb. 19:12 ro 0h reserved (rsvd) 11 rw-l 0b uncore me stolen memory enable (me_stlen_en) indicates whether the intel me stolen memory range is enabled or not. 10 rw-kl 0b uncore me range lock (melck) this field indicates whether a ll bits in the meseg_base and meseg_mask registers are locked. when locked, updates to any field for these registers must be dropped. 9:0 ro 0h reserved (rsvd) datasheet, volume 2 65 processor configuration registers 2.5.21 pam0?programmable attribute map 0 register this register controls the read, write and sh adowing attributes of the bios range from f_0000h to f_ffffh. the uncore allows prog rammable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlle d using the mtrr register in the core. two bits are used to specify memory attrib utes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 80h reset value: 00h access: rw size: 8 bits bios optimal default 00h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0f0000?0fffff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0f_0000h to 0f_ffffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are sent to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:0 ro 0h reserved (rsvd) processor configuration registers 66 datasheet, volume 2 2.5.22 pam1?programmable attribute map 1 register this register controls the read, write and sh adowing attributes of the bios range from c_0000h to c_7fffh. the uncore allows pr ogrammable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled using the mtrr register in the core. two bits are used to specify memory attributes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 81h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0c4000?0c7fff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0c_4000h to 0c_7fffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are se nt to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0c0000?0c3fff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0c0000h to 0c3fffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are se nt to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. datasheet, volume 2 67 processor configuration registers 2.5.23 pam2?programmable attribute map 2 register this register controls the read, write and sh adowing attributes of the bios range from c_8000h to c_ffffh. the uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlle d using the mtrr register in the core. two bits are used to specify memory attrib utes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 82h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0cc000?0cffff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0cc000h to 0cffffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are sent to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0c8000?0cbfff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0c8000h to 0cbfffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are sent to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. processor configuration registers 68 datasheet, volume 2 2.5.24 pam3?programmable attribute map 3 register this register controls the read, write and sh adowing attributes of the bios range from d0000h to d7fffh. the uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled using the mtrr register in the core. two bits are used to specify memory attributes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 83h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0d4000?0d7fff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0d4000h to 0d7fffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are se nt to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0d0000?0d3fff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0d0000h to 0d3fffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are se nt to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. datasheet, volume 2 69 processor configuration registers 2.5.25 pam4?programmable attribute map 4 register this register controls the read, write and sh adowing attributes of the bios range from d8000h to dffffh. the uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlle d using the mtrr register in the core. two bits are used to specify memory attrib utes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 84h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0dc000?0dffff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0dc000h to 0dffffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are sent to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0d8000?0dbfff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0d8000h to 0dbfffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are sent to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. processor configuration registers 70 datasheet, volume 2 2.5.26 pam5?programmable attribute map 5 register this register controls the read, write and sh adowing attributes of the bios range from e_0000h to e_7fffh. the uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled using the mtrr register in the core. two bits are used to specify memory attributes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 85h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0e4000?0e7fff attribute (hienable) this field controls the steering of read and write cycles that address the bios area from 0e4000h to 0e7fffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are se nt to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0e0000?0e3fff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0e0000h to 0e3fffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are se nt to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. datasheet, volume 2 71 processor configuration registers 2.5.27 pam6?programmable attribute map 6 register this register controls the read, write and sh adowing attributes of the bios range from e_8000h to e_ffffh. the uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlle d using the mtrr register in the core. two bits are used to specify memory attrib utes for each memory segment. these bits apply to host accesses to the pam areas. these attributes are: ? re ? read enable. when re=1, the host read accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when re=0, the host read accesses are directed to dmi. ? we ? write enable. when we=1, the host write accesses to the corresponding memory segment are claimed by the un core and directed to main memory. conversely, when we=0, the host read accesses are directed to dmi. the re and we attributes permit a memory segment to be read only, write only, read/write or disabled. for example, if a memory segment has re=1 and we=0, the segment is read only. b/d/f/type: 0/0/0/pci address offset: 86h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:6 ro 0h reserved (rsvd) 5:4 rw 00b uncore 0ec000?0effff attribute (hienable) this field controls the steering of read and write cycles that address the bios area fr om 0ec000h to 0effffh. 00 = dram disabled. all accesses are directed to dmi. 01 = read only. all reads are sent to dram, all writes are forwarded to dmi. 10 = write only. all writes are sent to dram, all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. 3:2 ro 0h reserved (rsvd) 1:0 rw 00b uncore 0e8000?0ebfff attribute (loenable) this field controls the steering of read and write cycles that address the bios area from 0e8000h to 0ebfffh. 00 = dram disabled. all reads are sent to dram. all writes are forwarded to dmi. 01 = read only. all reads are sent to dram. all writes are forwarded to dmi. 10 = write only. all writes are sent to dram. all reads are serviced by dmi. 11 = normal dram operation. all reads and writes are serviced by dram. this register is locked by intel txt. processor configuration registers 72 datasheet, volume 2 2.5.28 lac?legacy acce ss control register this 8-bit register controls steering of mda cycles and a fixed dram hole from 15? 16 mb. there can only be at most one mda device in the system. b/d/f/type: 0/0/0/pci address offset: 87h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7rw 0buncore hole enable (hen) this field enables a memory hole in dram space. the dram that lies "behind" this sp ace is not remapped. 0 = no memory hole. 1 = memory hole from 15 mb to 16 mb. this bit is intel txt lockable. 6:4 ro 0h reserved (rsvd) 3rw 0buncore peg60 mda present (mdap60) this bit works with the vga enable bits in the bctrl register of device 6 function 0 to control the routing of processor initiated transactions targeting mda comp atible i/o and memory address ranges. this bit should not be set if device 6 vga enable bit is not set. if device 6 function 0 vga enable bi t is not set, then accesses to i/o address range x3bch-x3bfh remain on the backbone. if the vga enable bit is set and mda is not present, then accesses to i/o address range x3bch-x3bfh are forwarded to pci express* through device 6 function 0 if the address is within the corresponding iobase and iolimit, otherwise they remain on the backbone. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h , 3b9h, 3bah, 3bfh, (including isa address a liases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations listed above, or their aliases, will remain on the backbone even if the reference also includes i/o locations not listed above. the following table shows the beha vior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are not claimed by device 6 function 0. 0 1 illegal combination 1 0 all vga and mda references are routed to pci express graphics attach device 6 function 0. 1 1 all vga references are routed to pci express graphics attach device 6 function 0. mda references are not claimed by device 6 function 0. vga and mda memory cycles can only be routed across peg60 when mae (pcicmd60[1]) is set. vga and mda i/o cycles can only be routed across peg60 if ioae (pcicmd60[0]) is set. 0 = no mda 1 = mda present datasheet, volume 2 73 processor configuration registers 2rw 0buncore peg12 mda present (mdap12) this bit works with the vga enable bits in the bctrl register of device 1 function 2 to control the routing of processor initiated transactions targeting mda comp atible i/o and memory address ranges. this bit should not be set if device 1 function 2 vga enable bit is not set. if device 1 function 2 vga enable bit is not set, then accesses to i/o address range x3bch-x3bfh remain on the backbone. if the vga enable bit is set and mda is not present, then accesses to i/o address range x3bch?x3bfh are forwarded to pci express through device 1 function 2 if the address is within the corresponding iobase and iolimit, otherwise they remain on the backbone. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes th e i/o locations listed above, or their aliases, will remain on the backbone even if the reference also includes i/o locations not listed above. the following table shows the beha vior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are not claimed by device 1 function 2. 0 1 illegal combination 1 0 all vga and mda references are routed to pci express graphics attach device 1 function 2. 1 1 all vga references are routed to pci express graphics attach device 1 function 2. mda references are not claimed by device 1 function 2. vga and mda memory cycles can only be routed across peg12 when mae (pcicmd12[1]) is set. vga and mda i/o cycles can only be routed across peg12 if ioae (pcicmd12[0]) is set. b/d/f/type: 0/0/0/pci address offset: 87h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 74 datasheet, volume 2 1rw 0buncore peg11 mda present (mdap11) this bit works with the vga enable bits in the bctrl register of device 1 function 1 to control the routing of processor initiated transactions targeting mda comp atible i/o and memory address ranges. this bit should not be set if device 1 function 1 vga enable bit is not set. if device 1 function 1 vga enable bi t is not set, then accesses to i/o address range x3bch-x3bfh remain on the backbone. if the vga enable bit is set and mda is not present, then accesses to i/o address range x3bch-x3bfh are forwarded to pci express* through device 1 function 1 if the address is within the corresponding iobase and iolimit, otherwise they remain on the backbone. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h , 3b9h, 3bah, 3bfh, (including isa address a liases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations listed above, or their aliases, will remain on the backbone even if the reference also includes i/o locations not listed above. the following table shows the beha vior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are not claimed by device 1 function 1. 0 1 illegal combination 1 0 all vga and mda references are routed to pci express graphics attach device 1 function 1. 1 1 all vga references are routed to pci express graphics attach device 1 function 1. mda references are not claimed by device 1 function 1. vga and mda memory cycles can only be routed across peg11 when mae (pcicmd11[1]) is set. vga and mda i/o cycles can only be routed across peg11 if ioae (pcicmd11[0]) is set. b/d/f/type: 0/0/0/pci address offset: 87h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description datasheet, volume 2 75 processor configuration registers 0rw 0buncore peg10 mda present (mdap10) this bit works with the vga enable bits in the bctrl register of device 1 function 0 to control the routing of processor initiated transactions targeting mda comp atible i/o and memory address ranges. this bit should not be set if device 1 function 0 vga enable bit is not set. if device 1 function 0 vga enable bit is not set, then accesses to i/o address range x3bch?x3bfh remain on the backbone. if the vga enable bit is set and mda is not present, then accesses to i/o address range x3bch?x3bfh are forwarded to pci express through device 1 function 0 if the address is within the corresponding iobase and iolimit, otherwise they remain on the backbone. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes th e i/o locations listed above, or their aliases, will remain on the backbone even if the reference also includes i/o locations not listed above. the following table shows the beha vior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are not claimed by device 1 function 0. 0 1 illegal combination 1 0 all vga and mda references are routed to pci express graphics attach device 1 function 0. 1 1 all vga references are routed to pci express graphics attach device 1 function 0. mda references are not cl aimed by device 1 function 0. vga and mda memory cycles can only be routed across peg10 when mae (pcicmd10[1]) is set. vga and mda i/o cycles can only be routed across peg10 if ioae (pcicmd10[0]) is set. b/d/f/type: 0/0/0/pci address offset: 87h reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 76 datasheet, volume 2 2.5.29 remapbase?remap base address register b/d/f/type: 0/0/0/pci address offset: 90?97h reset value: 0000000ffff00000h access: rw-l, rw-kl size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:36 ro 0h reserved (rsvd) 35:20 rw-l ffffh uncore remap base address (remapbase) the value in this register defines the lower boundary of the remap window. the remap window is inclusive of this address. in the decoder a[19:0] of the remap base address are assumed to be 0s. thus the bottom of th e defined memory range will be aligned to a 1 mb boundary. when the value in this regist er is greater than the value programmed into the remap limit register, the remap window is disabled. these bits are intel txt lockable. 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. datasheet, volume 2 77 processor configuration registers 2.5.30 remaplimit?remap limit address register 2.5.31 tom?top of memory register this register contains the size of physical memory. bios determines the memory size reported to the os using this register. b/d/f/type: 0/0/0/pci address offset: 98?9fh reset value: 0000000000000000h access: rw-l, rw-kl size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:36 ro 0h reserved (rsvd) 35:20 rw-l 0000h uncore remap lim remap base register, the remap window is disabled. these bits are intel txt lockable. 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. b/d/f/type: 0/0/0/pci address offset: a0?a7h reset value: 0000007ffff00000h access: rw-l, rw-kl size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw-l 7ffffh uncore top of memory (tom) this register reflects the tota l amount of populated physical memory. this is not necessar ily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped io). these bits correspond to address bits 38:20 (1 mb granularity). bits 19:0 are assumed to be 0. all the bits in this register are locked in intel txt mode. 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. processor configuration registers 78 datasheet, volume 2 2.5.32 touud?top of upper usable dram register this 64 bit register defines the top of upper usable dram. configuration software must set this value to tom minus all intel me stolen memory if reclaim is disabled. if reclaim is enabled, this value must be set to reclaim limit + 1 byte, 1 mb aligned, since reclaim limit is 1 mb aligned. address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register and greater than or equal to 4 gb. bios restriction: minimum value for touud is 4 gb. these bits are intel txt lockable. b/d/f/type: 0/0/0/pci address offset: a8?afh reset value: 0000000000000000h access: rw-kl, rw-l size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw-l 00000h uncore touud (touud) this register contains bits 38:20 of an address one byte above the maximum dram memory above 4 gb that is usable by the operating system. configuration software must set this value to tom minus all intel me stolen memory if reclaim is disabled. if reclaim is enabled, this value must be set to reclaim limit 1 mb aligned since reclaim limit + 1byte is 1 mb aligned. address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register and greater than 4 gb. all the bits in this register are locked in intel txt mode. 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. datasheet, volume 2 79 processor configuration registers 2.5.33 bdsm?base data of stolen memory register this register contains the base address of graphics data stolen dram memory. bios determines the base of graphics data stol en memory by subtracting the graphics data stolen memory size (pci device 0 offset 52 bits 7:4) from tolud (pci device 0 offset bch bits 31:20). 2.5.34 bgsm?base of gtt stolen memory register this register contains the base address of stolen dram memory for the gtt. bios determines the base of gtt stolen memory by subtracting the gtt graphics stolen memory size (pci device 0 offset 52h bits 9:8) from the graphics base of data stolen memory (pci device 0 offset b0h bits 31:20). b/d/f/type: 0/0/0/pci address offset: b0?b3h reset value: 00000000h access: rw-kl, rw-l size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw-l 000h uncore graphics base of stolen memory (bdsm): this register contains bits 31:20 of the base address of stolen dram memory. bios determines the base of graphics stolen memory by subtracting the graphics stolen memory size (pci device 0 offset 52 bits 6:4) from tolud (pci device 0 offset bch bits 31:20). 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. b/d/f/type: 0/0/0/pci address offset: b4?b7h reset value: 00100000h access: rw-l, rw-kl size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw-l 001h uncore graphics base of gtt stolen memory (bgsm) this register contains the base address of stolen dram memory for the gtt. bios determines the base of gtt stolen memory by subtracting the gtt graphics stolen memory size (pci device 0 offset 52h bits 11:8) from the graphics base of data stolen memory (pci device 0 offset b0h bits 31:20). 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. processor configuration registers 80 datasheet, volume 2 2.5.35 tsegmb?tseg memory base register this register contains the base address of tseg dram memory. bios determines the base of tseg memory which must be at or below graphics base of gtt stolen memory (pci device 0 offset b4h bits 31:20). note: bios must program tsegmb to an 8 mb naturally aligned boundary. 2.5.36 tolud?top of low usable dram register this 32 bit register defines the top of low usable dram. tseg, gtt graphics memory and graphics stolen memory are within the dram space defined. from the top, the host optionally claims 1 to 64 mb of dram fo r internal graphics if enabled, 1 or 2 mb of dram for gtt graphics stolen memory (if enabled) and 1, 2, or 8 mb of dram for tseg if enabled. programming example: c1drb3 is set to 4 gb tseg is enabled and tseg size is set to 1 mb internal graphics is enabled, and graphics mode select is set to 32 mb gtt graphics stolen memory size set to 2 mb bios knows the os requires 1 gb of pci space. bios also knows the range from 0_fec 0_0000h to 0_ffff_ffffh is not usable by the system. this 20 mb range at th e very top of addressable memory space is lost to apic and intel txt. according to the above equation, tolud is originally calculated to: 4 gb = 1_0000_0000h the system memory requirements are: 4 gb (max addressable space) ? 1g b (pci space) ? 35 mb (lost memory) = 3 gb ? 35 mb (minimum granularity) = 0_ecb0_0000h since 0_ecb0_0000h (pci and other system requirements) is less than 1_0000_0000h, tolud should be programmed to ecbh. these bits are intel txt lockable. b/d/f/type: 0/0/0/pci address offset: b8?bbh reset value: 00000000h access: rw-l, rw-kl size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw-l 000h uncore tesg memory base (tsegmb) this register contains the base address of tseg dram memory. bios determines the base of tseg memory which must be at or below graphics base of gtt stolen memory (pci device 0 offset b4h bits 31:20). 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock) this bit will lock all writeable se ttings in this register, including itself. datasheet, volume 2 81 processor configuration registers 2.5.37 skpd?scratchpad data register this register holds 32 writable bits with no functionality behind them. it is for the convenience of bios and graphics drivers. b/d/f/type: 0/0/0/pci address offset: bc?bfh reset value: 00100000h access: rw-kl, rw-l size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw-l 001h uncore top of low usable dram (tolud) this register contains bits 31:20 of an address one byte above the maximum dram memory below 4 gb that is usable by the operating system. address bits 31:20 programmed to 01h implies a minimum memory size of 1 mb. configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the sy stem minus intel me stolen memory plus one byte or the minimum address allocated for pci memory. address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register. the top of low usable dram is the lowest address above both graphics stolen memory and tseg. bios determines the base of graphics stolen memory by subtracting the graphics stolen memory size from tolud and further decrements by tseg size to determine base of tseg. all the bits in this register are locked in intel txt mode. this register must be 1 mb aligned when reclaim is enabled. 19:1 ro 0h reserved (rsvd) 0rw-kl 0b uncore lock (lock): this bit will lock all writeable se ttings in this register, including itself. b/d/f/type: 0/0/0/pci address offset: dc?dfh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore scratchpad data (skpd) 1 dword of data storage. processor configuration registers 82 datasheet, volume 2 2.5.38 capid0_a?capabilities a register this register control of bits in this register are only required for customer visible sku differentiation. b/d/f/type: 0/0/0/pci address offset: e4?e7h reset value: 00000000h access: ro-fw, ro-kfw size: 32 bits bios optimal default: 000000h bit access reset value rst/ pwr description 31 ro-kfw 0b reserved (rsvd) 30 ro-kfw 0b reserved (rsvd) 29 ro-kfw 0b reserved (rsvd) 28 ro-kfw 0b reserved (rsvd) 27 ro-fw 0b reserved (rsvd) 26 ro-fw 0b reserved (rsvd) 25 ro-fw 0b uncore ecc disable (eccdis) 0 = ecc capable 1 = not ecc capable 24 ro-fw 0b reserved (rsvd) 23 ro-kfw 0b uncore vtd disable (vtdd) 0 = enable vtd 1 = disable vtd 22 ro-fw 0b reserved (rsvd) 21 ro-fw 0b reserved (rsvd) 20:19 ro-fw 00b reserved (rsvd) 18 ro-fw 0b reserved (rsvd) 17 ro-fw 0b reserved (rsvd) 16 ro-fw 0b reserved (rsvd) 15 ro-kfw 0b reserved (rsvd) 14 ro-fw 0b uncore 2 dimms per channel disable (ddpcd) this bit allows dual channel operation but only supports 1 dimm per channel. 0 = 2 dimms per channel enabled 1 = 2 dimms per channel disabled. this setting hardwires bits 2 and 3 of the rank population field for each channel to zero. (mchbar offset 260h, bits 22:23 for channel 0 and mchbar offset 660h, bits 22:23 for channel 1) 13 ro-fw 0b reserved (rsvd) 12 ro-fw 0b reserved (rsvd) 11 ro-kfw 0b reserved (rsvd) 10 ro-fw 0b reserved (rsvd) 9:8 ro-fw 00b reserved (rsvd) 7:4 ro-fw 0h reserved (rsvd) datasheet, volume 2 83 processor configuration registers 2ro-fw0buncore ia overclocking enabled by dsku (oc_enabled_dsku) the default constant (non-fuse) value is zero. when the vdm sets this bit, oc will be ap plied if oc_ctl_ssku points to dsku. 1ro-fw0buncore on-die ddr write vref generation allowed (ddr_wrtvref) this bit allow on-die dd r write vref generation. pcode will update this field with the value of fuse_ddr_wrtvref. 0ro-fw0buncore ddr3l (1.35v ddr) operation allowed (ddr3l_en) this bit allows ddr3l (1.35v ddr) operation. pcode will update this field with the value of fuse_ddr3l_en. 1.35 v (voltage level) for ddr3 is not supported or validated by intel on the intel ? xeon ? processor e3- 1200 v2 product family. b/d/f/type: 0/0/0/pci address offset: e4?e7h reset value: 00000000h access: ro-fw, ro-kfw size: 32 bits bios optimal default: 000000h bit access reset value rst/ pwr description processor configuration registers 84 datasheet, volume 2 2.5.39 capid0_b?capabilities b register control of bits in this register are only re quired for customer visible sku differentiation. b/d/f/type: 0/0/0/pci address offset: e8-ebh default value: 00100000h access: ro-fw, ro-kfw size: 32 bits bios optimal default: 000000h bit access reset value rst/ pwr description 31 ro-fw 0h reserved (rsvd) 30 ro-fw 0b reserved (rsvd) 29 ro-fw 0b reserved (rsvd) 28 ro-fw 0b uncore smt capability (smt) this setting indicates whether or not the processor is smt capable. 27:25 ro-fw 000b uncore cache size capability (cachesz) this setting indicates the supporting cache sizes. 24 ro-fw 0b reserved (rsvd) 23:21 ro-fw 000b uncore ddr3 maximum frequency capa bility with 100 memory (pll_ref100_cfg) ddr3 maximum frequency capability with 100 mhz memory. pcode will update this field with the value of fuse_pll_ref100_cfg and then apply ssku overrides. maximum allowed memory frequency with 100 mhz reference clock. also serves as defeature. unlike 133 mhz reference fuses, these are normal 3-bit fields. 0 = 100 mhz ref disabled 1 = up to ddr-1400 (7 x 200) 2 = up to ddr-1600 (8 x 200) 3 = up to ddr-1800 (8 x 200) 4 = up to ddr-2000 (10 x 200) 5 = up to ddr-2200 (11 x 200) 6 = up to ddr-2400 (12 x 200) 7 = no limit (but still limi ted by %max_ddr_freq200 to 2600) 20 ro-fw 0b uncore pcie gen 3 disable (pegg3_dis) pcode will update this field with the value of fuse_pegg3_dis and then apply ssku overrides. this is a defeature fuse ? an un-programmed device should have pcie gen 3 capabilities enabled. 0 = capable of running any of the gen 3-compliant peg controllers in gen 3 mode (devices 0/1/0, 0/1/1, 0/1/2) 1 = not capable of running any of the peg controllers in gen 3 mode 19 ro-fw 0b reserved (rsvd) 18 ro-fw 0b uncore additive graphics enabled (addgfxen) 0 = additive graphics disabled 1 = additive graphics enabled 17 ro-fw 0b uncore additive graphics capable (addgfxcap) 0 = capable of additive graphics 1 = not capable of additive graphics 16 ro-fw 0b reserved (rsvd) 15:12 ro-fw 0h reserved (rsvd) datasheet, volume 2 85 processor configuration registers 11 ro-fw 0b reserved (rsvd) 10:8 ro-fw 000b reserved (rsvd) 7ro-fw 0b reserved (rsvd) 6:4 ro-fw 000b uncore ddr3 maximum frequency capability (dmfc) pcode will update this field wi th the value of fuse_dmfc, and then apply ssku overrides. maximum allowed memory frequency with 133 mhz reference clock. this is a reversed 3-bit field: 7 = up to ddr-1066 (4 x 266) 6 = up to ddr-1333 (5 x 266) 5 = up to ddr-1600 (6 x 266) 4 = up to ddr-1866 (7 x 266) 3 = up to ddr-2133 (8 x 266) 2 = up to ddr-2400 (9 x 266) 1 = up to ddr-2666 (10 x 266) 0 = up to ddr-2933 (11 x 266) -- reserved fuse value; not really supported; 3ro-fw 0b reserved (rsvd) 2ro-fw 0b reserved (rsvd) 1ro-fw 0b reserved (rsvd) 0ro-fw 0b reserved (rsvd) b/d/f/type: 0/0/0/pci address offset: e8-ebh default value: 00100000h access: ro-fw, ro-kfw size: 32 bits bios optimal default: 000000h bit access reset value rst/ pwr description processor configuration registers 86 datasheet, volume 2 2.5.40 errsts?error status register this register is used to report various error conditions using the serr dmi messaging mechanism. an serr dmi message is generated on a zero to one transition of any of these flags (if enabled by the errcmd and pcicmd registers). these bits are set regardless of whether or not the serr is enabled and generated. after the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a '1' to it. b/d/f/type: 0/0/0/pci address offset: c8?c9h reset value: 0000h access: rw1cs size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1 rw1cs 0b powergood multiple-bit dram e cc error flag (dmerr) if this bit is set to 1, a memory read data transfer had an uncorrectable multiple-bit error. wh en this bit is set, the column, row, bank, and rank that caused the error, and the error syndrome, are logged in the ecc error log register in the channel where the error occurred. once this bit is set, the eccerrlogx fields are locked until the processor clears this bit by writing a 1. softwa re uses bits [1:0] to detect whether the logged error address is for a sing le-bit or a multiple-bit error. this bit is reset on pwrok. 0 rw1cs 0b powergood single-bit dram ecc error flag (dserr) if this bit is set to 1, a memory read data transfer had a single- bit correctable error and the corrected data was returned to the requesting agent. when this bit is set the column, row, bank, and rank where the error occurred and the syndrome of the error are logged in the ecc error log register in the channel where the error occurred. once this bit is set the eccerrlogx fields are locked to further single-bit error updates until the processor clears this bit by writing a 1. a multiple bit error that occurs after this bit is set will overwrite the eccerrlogx fields with the multiple-bit error sign ature and the dmerr bit will also be set. a single bit error that occurs after a multibit error will set this bit but will not overwrite the other fields. this bit is reset on pwrok. datasheet, volume 2 87 processor configuration registers 2.5.41 errcmd?error command register this register controls the host bridge responses to various system errors. since the host bridge does not have an serr# signal, serr messages are passed from the processor to the pch over dmi. when a bit in this register is set, a serr message will be generated on dmi whenever the corresponding flag is set in the errsts register. the actual generation of the serr message is globally enabled for devi ce 0 using the pci command register. b/d/f/type: 0/0/0/pci address offset: ca?cbh reset value: 0000h access: rw size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1rw 0buncore serr multiple-bit dram ecc error (dmerr) 1 = the host bridge generates an serr message over dmi when it detects a multiple-bit e rror reported by the dram controller. 0 = reporting of this condit ion using serr messaging is disabled. for systems not supporting ecc, this bit must be disabled. 0rw 0buncore serr on single-bit ecc error (dserr) 1 = the host bridge generates an serr special cycle over dmi when the dram controller detects a single bit error. 0 = reporting of this condit ion using serr messaging is disabled. for systems that do not support ecc, this bit must be disabled. processor configuration registers 88 datasheet, volume 2 2.5.42 smicmd?smi command register this register enables various errors to generate an smi dmi special cycle. when an error flag is set in the errsts register, it can generate an serr, smi, or sci dmi special cycle when enabled in the errcmd, smicmd, or scicmd registers, respectively. note: only one message type can be enabled. 2.5.43 scicmd?sci command register this register enables various errors to generate an smi dmi special cycle. when an error flag is set in the errsts register, it can generate an serr, smi, or sci dmi special cycle when enabled in the errcmd, smicmd, or scicmd registers, respectively. note: only one message type can be enabled. b/d/f/type: 0/0/0/pci address offset: cc?cdh reset value: 0000h access: rw size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1rw 0buncore smi on multiple-bit dram ecc error (dmesmi) 1 = the host generates an smi dmi message when it detects a multiple-bit error reported by the dram controller. 0 = reporting of this condition using smi messaging is disabled. for systems not supporting ecc, this bit must be disabled. 0rw 0buncore smi on single-bit ecc error (dsesmi) 1 = the host generates an smi dmi special cycle when the dram controller detects a single bit error. 0 = reporting of this condition using smi messaging is disabled. for systems that do not support e cc, this bit must be disabled. b/d/f/type: 0/0/0/pci address offset: ce?cfh reset value: 0000h access: rw size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1rw 0buncore sci on multiple-bit dram ecc error (dmesci) 1 = the host generates an sci dmi message when it detects a multiple-bit error reported by the dram controller. 0 = reporting of this condition using sci messaging is disabled. for systems not supporting ecc, this bit must be disabled. 0rw 0buncore sci on single-bit ecc error (dsesci) 1 = the host generates an sci dmi special cycle when the dram controller detects a single bit error. 0 = reporting of this condition using sci messaging is disabled. for systems that do not support e cc, this bit must be disabled. datasheet, volume 2 89 processor configuration registers 2.6 pci device 1 function 0 configuration space registers table 2-9. pci device 1 function 0 configurat ion space register address map (sheet 1 of 2) address offset register symbol register name reset value access 0?1h vid vendor identification 8086h ro 2?3h did device identification 0151h ro-fw 4?5h pcicmd pci command 0000h ro, rw 6?7h pcists pci status 0010h ro, rw1c, ro-v 8h rid revision identification 00h ro-fw 9?bh cc class code 060400h ro ch cl cache line size 00h rw dh rsvd reserved 0h ro eh hdr header type 81h ro f?17h rsvd reserved 0h ro 18h pbusn primary bus number 00h ro 19h sbusn secondary bus number 00h rw 1ah subusn subordinate bus number 00h rw 1bh rsvd reserved 0h ro 1ch iobase i/o base address f0h rw 1dh iolimit i/o limit address 00h rw 1e?1fh ssts secondary status 0000h rw1c, ro 20?21h mbase memory base address fff0h rw 22?23h mlimit memory limit address 0000h rw 24?25h pmbase prefetchable memory base address fff1h ro, rw 26?27h pmlimit prefetchable memory limit address 0001h rw, ro 28?2bh pmbaseu prefetchable memory base address upper 00000000h rw 2c?2fh pmlimitu prefetchable memory limit address upper 00000000h rw 30?33h rsvd reserved 0h ro 34h capptr capabilities pointer 88h ro 35?3bh rsvd reserved 0h ro 3ch intrline interrupt line 00h rw 3dh intrpin interrupt pin 01h rw-o, ro 3e?3fh bctrl bridge control 0000h ro, rw 40?7fh rsvd reserved 0h ro 80?83h pm_capid power management capabilities c8039001h ro, ro-v 84?87h pm_cs power management control/status 00000008h ro, rw 88?8bh ss_capid subsystem id and vendor id capabilities 0000800dh ro 8c?8fh ss subsystem id and su bsystem vendor id 00008086h rw-o 90?91h msi_capid message signaled interrupts capability id a005h ro processor configuration registers 90 datasheet, volume 2 2.6.1 vid?vendor identification register this register, combined with the device identification register, uniquely identify any pci device. 92?93h mc message control 0000h rw, ro 94?97h ma message address 00000000h rw, ro 98?99h md message data 0000h rw 9a?9fh rsvd reserved 0h ro a0?a1h peg_capl pci express-g capability list 0010h ro a2?a3h peg_cap pci express-g capabilities 0142h ro, rw-o a4?a7h dcap device capabilities 00008000h ro, rw-o a8?a9h dctl device control 0020h ro, rw aa?abh dsts device status 0000h rw1c, ro ac?afh lcap link capabilities 0261cd03h ro, ro-v, rw-o, rw-ov b0?b1h lctl link control 0000h rw, ro, rw-v b2?b3h lsts link status 1001h rw1c, ro-v, ro b4?b7h slotcap slot capabilities 00040000h rw-o, ro b8?b9h slotctl slot control 0000h ro ba?bbh slotsts slot status 0000h ro, rw1c, ro-v bc?bdh rctl root control 0000h ro, rw be?bfh rsvd reserved 0h ro c0?c3h rsts root status 00000000h ro, rw1c, ro-v c4?c7h dcap2 device capabilities 2 00000800h ro, rw-o c8?c9h dctl2 device control 2 0000h rw-v, rw ca?cbh rsvd reserved 0h ro cc?cfh lcap2 link capabilities 2 0000000eh ro-v d0?d1h lctl2 link control 2 0003h rws, rws-v d2?d3h lsts2 link status 2 0000h ro-v, rw1c table 2-9. pci device 1 function 0 configuration space regist er address map (sheet 2 of 2) address offset register symbol register name reset value access b/d/f/type: 0/1/0/pci address offset: 0?1h reset value: 8086h access: ro size: 16 bits bit access reset value rst/ pwr description 15:0 ro 8086h uncore vendor identification (vid) pci standard identification for intel. datasheet, volume 2 91 processor configuration registers 2.6.2 did?device identification register this register combined with the vendor identification register uniquely identifies any pci device. 2.6.3 pcicmd?pci command register b/d/f/type: 0/1/0/pci address offset: 2?3h reset value: 0151h access: ro-fw size: 16 bits bit access reset value rst/ pwr description 15:0 ro-fw 0151h uncore device identification number msb (did_msb) identifier assigned to the processor root port (virtual pci-to-pci bridge, pci express graphics port). b/d/f/type: 0/1/0/pci address offset: 4?5h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:11 ro 0h reserved (rsvd) 10 rw 0b uncore inta assertion disable (intaad) 0 = this device is permitted to generate inta interrupt messages. 1 = this device is prevented from generating interrupt messages. any inta emulation interrupts already asserted must be de-asserted when this bit is set. this bit only affects interrupts ge nerated by the device (pci inta from a pme or hot-plug event) controlled by this command register. it does not affect up stream msis, upstream pci inta- intd assert and deassert messages. note: pci express* hot-plug is not supported on the processor. 9ro 0buncore fast back-to-back enable (fb2b) not applicable or impleme nted. hardwired to 0. processor configuration registers 92 datasheet, volume 2 8rw 0buncore serr# message enable (serre) this bit controls the root port's serr# messaging. the processor communicates the serr# cond ition by sending an serr message to the pch. this bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the root complex. note that errors are reported if enabled either through this bit or through the pci expres s* specific bits in the device control register. in addition, for type 1 configuration space header devices, this bit, when set, enables transmissi on by the primary interface of err_nonfatal and err_fatal error messages forwarded from the secondary interface. this bit does not affect the transmission of forwarded err_cor messages. 0 = the serr message is generated by the root port only under conditions enabled in dividually through the device control register. 1 = the root port is enabled to generate serr messages which will be sent to the pch for specif ic root port error conditions generated/detected or received on the secondary side of the virtual pci to pci bridge. the status of serrs generated is reported in the pcists register. 7ro 0h reserved (rsvd) 6rw 0buncore parity error respons e enable (perre) this bit controls whether or not the master data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register can not be set. 1 = master data parity error bit in pci status register can be set. 5ro 0buncore vga palette snoop (vgaps) not applicable or implem ented. hardwired to 0. 4ro 0buncore memory write and invalidate enable (mwie) not applicable or implem ented. hardwired to 0. 3ro 0buncore special cycle enable (sce) not applicable or implem ented. hardwired to 0. 2rw 0buncore bus master enable (bme ) this bit controls the ability of the peg port to forward memory read/write requests in the upstream direction. 0 = this device is prevented from making memory requests to its primary bus. note that according to pci specification, as msi interrupt messages ar e in-band memory writes, disabling the bus master enable bit prevents this device from generating msi interrupt messages or passing them from its secondary bus to its primary bus. upstream memory writes/reads, peer wr ites/reads, and msis will all be treated as illegal cycles. wr ites are aborted. reads are aborted and will return unsupported request status (or master abort) in its completion packet. 1 = this device is allowed to issue requests to its primary bus. completions for previously issued memory read requests on the primary bus will be issued when the data is available. this bit does not affect forwarding of completions from the primary interface to the secondary interface. b/d/f/type: 0/1/0/pci address offset: 4?5h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description datasheet, volume 2 93 processor configuration registers 2.6.4 pcists?pci status register this register reports the occurrence of error conditions associated with primary side of the "virtual" host-pci express* bridge embedded within the root port. 1rw 0buncore memory access enable (mae ) 0 = all of device's memory space is disabled. 1 = enable the memory and pre-fetchable memory address ranges defined in the mbase, mlimit, pmbase, and pmlimit registers. 0rw 0buncore io access enable (ioae ) 0 = all of device?s i/o space is disabled. 1 = enable the i/o address range defined in the iobase, and iolimit registers. b/d/f/type: 0/1/0/pci address offset: 4?5h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description b/d/f/type: 0/1/0/pci address offset: 6?7h reset value: 0010h access: ro, rw1c, ro-v size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 rw1c 0b uncore detected parity error (dpe) this bit is set by a function whenever it receives a poisoned tlp, regardless of the state the parity error response bit in the command register. on a function with a type 1 configuration header, the bit is set when the poisoned tlp is received by its primary side. reset value of this bit is 0b. this bit will be set only for completions of requests encountering ecc error in dram. poisoned peer-to-peer posted forw arded will not set this bit. they are reported at the receiving port. 14 rw1c 0b uncore signaled system error (sse) this bit is set when this device sends an serr due to detecting an err_fatal or err_nonfatal condition and the serr enable bit in the command register is '1 '. both received (if enabled by bctrl1[1]) and internally detected error messages do not affect this field. 13 ro 0b uncore received master abort status (rmas) this bit is set when a requester receives a completion with unsupported request completion status. on a function with a type 1 configuration header, the bit is set when the unsupported request is received by its primary side. not applicable. ur not on primary interface. processor configuration registers 94 datasheet, volume 2 12 ro 0b uncore received target abort status (rtas ) this bit is set when a requester receives a completion with completer abort completion status. on a function with a type 1 configuration header, the bit is set when the completer abort is received by its primary side. reset value of this bit is 0b. not applicable or implemented. ha rdwired to 0. the concept of a completer abort does not exist on primary side of this device. 11 ro 0b uncore signaled target abort status (stas) this bit is set when a function completes a posted or non-posted request as a completer abort error. this applies to a function with a type 1 configuration header when the completer abort was generated by its primary side. reset value of this bit is 0b. not applicable or implemented. ha rdwired to 0. the concept of a target abort does not exist on primary side of this device. 10:9 ro 00b uncore devselb timing (devt) this device is not the subtractively decoded device on bus 0. this bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. does not apply to pci express and must be hardwired to 00b. 8rw1c 0b uncore master data parity error (pmdpe) this bit is set by a requester (primary side for type 1 configuration space header function) if the party error response bit in the command register is 1b and either of the following two conditions occurs: ? requester receives a co mpletion marked poisoned ? requester poisons a write request if the parity error response bit is 0b, this bit is never set. reset value of this bit is 0b. this bit will be set only for comple tions of requests encountering ecc error in dram. poisoned peer-to-peer posted forw arded will not set this bit. they are reported at the receiving port. 7ro 0buncore fast back-to-back (fb2b ) not applicable or implem ented. hardwired to 0. 6ro 0h reserved (rsvd) 5ro 0buncore 66/60mhz capability (cap66) not applicable or implem ented. hardwired to 0. 4ro 1buncore capabilities list (capl ) indicates that a capabilities list is present. hardwired to 1. 3ro-v 0b uncore intx status (intas) this bit indicates that an interru pt message is pe nding internally to the device. only pme and hot-plug sources feed into this status bit (not pci inta?intd assert and deassert messages). the inta assertion disable bit, pcicmd1[10], has no effect on this bit. note: inta emulation interrupts received across the link are not reflected in this bit. note: pci express* hot-plug is not supported on the processor. 2:0 ro 0h reserved (rsvd) b/d/f/type: 0/1/0/pci address offset: 6?7h reset value: 0010h access: ro, rw1c, ro-v size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description datasheet, volume 2 95 processor configuration registers 2.6.5 rid?revision identification register this register contains the revision number of the processor root port. these bits are read only and writes to this register have no effect. 2.6.6 cc?class code register this register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. 2.6.7 cl?cache line size register b/d/f/type: 0/1/0/pci address offset: 8h reset value: 00h access: ro-fw size: 8 bits bit access reset value rst/ pwr description 7:0 ro-fw 0h uncore revision identification number (rid ) this is an 8-bit value that indi cates the revision identification number for the root port. refer to the intel ? xeon ? processor e3-1200 v2 product family specification update for the value of the rid register. b/d/f/type: 0/1/0/pci address offset: 9?bh reset value: 060400h access: ro size: 24 bits bit access reset value rst/ pwr description 23:16 ro 06h uncore base class code (bcc) this field indicates the base class code for this device. this code has the value 06h indica ting a bridge device. 15:8 ro 04h uncore sub-class code (subcc) this field indicates the sub-class code for this device. the code is 04h indicating a pci to pci bridge. 7:0 ro 00h uncore programming interface (pi) this field indicates the programmin g interface of this device. this value does not specify a particular register set layout and provides no practical use for this device. b/d/f/type: 0/1/0/pci address offset: ch reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore cache line size (cls ) implemented by pci express devices as a read-write field for legacy compatibility purposes but has no impact on any pci express device functionality. processor configuration registers 96 datasheet, volume 2 2.6.8 hdr?header type register this register identifies the header layout of the configuration space. no physical register exists at this location. 2.6.9 pbusn?primary bus number register this register identifies that this "virtual" host-pci express* bridge is connected to pci bus 0. 2.6.10 sbusn?secondary bus number register this register identifies the bus number assigned to the second bus side of the "virtual" bridge; that is, to pci express-g. this num ber is programmed by the pci configuration software to allow mapping of configuration cycles to pci express-g. b/d/f/type: 0/1/0/pci address offset: eh reset value: 81h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 81h uncore header type register (hdr) device 1 returns 81h to indicate that this is a multi function device with bridge header layout. device 6 returns 01h to indicate that this is a single function device with bridge header layout. b/d/f/type: 0/1/0/pci address offset: 18h reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore primary bus number (busn) configuration software typically programs this field with the number of the bus on the primary side of the bridge. since the processor root port is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. b/d/f/type: 0/1/0/pci address offset: 19h reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore secondary bus number (busn) this field is programmed by configuration software with the bus number assigned to pci express-g. datasheet, volume 2 97 processor configuration registers 2.6.11 subusn?subordinate bus number register this register identifies the subordinate bus (if any) that resides at the level below pci express-g. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci express-g. 2.6.12 iobase?i/o base address register this register controls the processor to pci express-g i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for th e purpose of address decode address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4 kb boundary. b/d/f/type: 0/1/0/pci address offset: 1ah reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore subordinate bus number (busn) this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the processor root port bridge. when only a single pci device resides on the pci express-g segment, this register will contain the same value as the sbusn1 register. b/d/f/type: 0/1/0/pci address offset: 1ch reset value: f0h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:4 rw fh uncore i/o address base (iobase) this field corresponds to a[15:12] of the i/o addresses passed by the root port to pci express-g. 3:0 ro 0h reserved (rsvd) processor configuration registers 98 datasheet, volume 2 2.6.13 iolimit?i/o limit address register this register controls the processor to pc i express-g i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are assumed to be fffh. thus, the to p of the defined i/o address range will be at the top of a 4 kb aligned address block. 2.6.14 ssts?secondary status register ssts is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, pc i express-g side) of the "virtual" pci-pci bridge embedded within the processor. b/d/f/type: 0/1/0/pci address offset: 1dh reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:4 rw 0h uncore i/o address limit (iolimit) this field corresponds to a[15:12] of the i/o address limit of the root port. devices be tween this upper limit and iobase1 will be passed to the pci express hierarchy associated with this device. 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/1/0/pci address offset: 1e?1fh reset value: 0000h access: rw1c, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15 rw1c 0b uncore detected parity error (dpe) this bit is set by the secondary side for a type 1 configuration space header device whenever it receives a poisoned tlp, regardless of the state of the parity error response enable bit in the bridge control register. 14 rw1c 0b uncore received system error (rse) this bit is set when the secondary side for a type 1 configuration space header device receives an err_fatal or err_nonfatal. 13 rw1c 0b uncore received master abort (rma) this bit is set when the secondar y side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a comple tion with unsupported request completion status. 12 rw1c 0b uncore received target abort (rta) this bit is set when the secondar y side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a comp letion with completer abort completion status. datasheet, volume 2 99 processor configuration registers 11 ro 0b uncore signaled target abort (sta) not applicable or implemented. hardwired to 0. the processor does not generate target abor ts (the root port will never complete a request using the completer abort completion status). ur detected inside the processo r (such as in imph/mc will be reported in primary side status) 10:9 ro 00b uncore devselb timing (devt) not applicable or impleme nted. hardwired to 0. 8rw1c 0b uncore master data parity error (smdpe) when set indicates that the processor received across the link (upstream) a read data comple tion poisoned tlp (ep=1). this bit can only be set when the parity error enable bit in the bridge control register is set. 7ro 0buncore fast back-to-back (fb2b) not applicable or impleme nted. hardwired to 0. 6ro 0h reserved (rsvd) 5ro 0buncore 66/60 mhz capability (cap66) not applicable or impleme nted. hardwired to 0. 4:0 ro 0h reserved (rsvd) b/d/f/type: 0/1/0/pci address offset: 1e?1fh reset value: 0000h access: rw1c, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 100 datasheet, volume 2 2.6.15 mbase?memory base address register this register controls the processor to pci express-g non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are re ad/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/1/0/pci address offset: 20?21h reset value: fff0h access: rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:4 rw fffh uncore memory address base (mbase) this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express-g. 3:0 ro 0h reserved (rsvd) datasheet, volume 2 101 processor configuration registers 2.6.16 mlimit?memory limit address register this register controls the processor to pci express-g non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read-only and return zeroes when read. th is register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: memory range covered by mbase and mlimit registers are used to map non- prefetchable pci express-g address ranges (typically where control/status memory- mapped i/o data structures of the graphics controller will reside) and pmbase and pmlimit are used to map prefetchable a ddress ranges (typically graphics local memory). this segregation allows applicatio n of uswc space attribute to be performed in a true plug-and-play manner to the pr efetchable address range for improved processor-pci express memory access performance. note: configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the va lues that provide exclusive address ranges; that is, prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the proc essor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured. b/d/f/type: 0/1/0/pci address offset: 22?23h reset value: 0000h access: rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:4 rw 000h uncore memory address limit (mlimit) this field corresponds to a[31: 20] of the upper limit of the address range passed to pci express-g. 3:0 ro 0h reserved (rsvd) processor configuration registers 102 datasheet, volume 2 2.6.17 pmbase?prefetchable me mory base address register this register in conjunction with the corresponding upper base address register controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/1/0/pci address offset: 24?25h reset value: fff1h access: ro, rw size: 16 bits bit access reset value rst/ pwr description 15:4 rw fffh uncore prefetchable memory base address (pmbase) this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express-g. 3:0 ro 1h uncore 64-bit address support (as64) this field indicates that the up per 32 bits of the prefetchable memory region base address are contained in the prefetchable memory base upper address register at 28h. datasheet, volume 2 103 processor configuration registers 2.6.18 pmlimit?prefetchable me mory limit address register this register, in conjunction with the corresponding upper limit address register, controls the processor to pci express-g pr efetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40-bit address. the lower 8 bi ts of the upper limit address register are read/write and correspond to address bits a[39 :32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be f ffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (that is, prefetchable) from the processor perspective. 2.6.19 pmbaseu?prefetchable memory base address upper register the functionality associated with this register is present in the peg design implementation. this register in conjunc tion with the corresponding upper base address register controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 39-bit address. the lower 7 bits of the upper base address register are read/write and correspond to address bits a[38 :32] of the 39-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/1/0/pci address offset: 26?27h reset value: 0001h access: rw, ro size: 16 bits bit access reset value rst/ pwr description 15:4 rw 000h uncore prefetchable memory address limit (pmlimit) this field corresponds to a[31: 20] of the upper limit of the address range passed to pci express* graphics. 3:0 ro 1h uncore 64-bit address support (as64b) this field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the prefetchable memory base limit address register at 2ch. b/d/f/type: 0/1/0/pci address offset: 28?2bh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 0000000 0h uncore prefetchable memory base address (pmbaseu) this field corresponds to a[63: 32] of the lower limit of the prefetchable memory range that will be passed to pci express-g. processor configuration registers 104 datasheet, volume 2 2.6.20 pmlimitu?prefe tchable memory limit address upper register the functionality associated with this register is present in the peg design implementation. this register in conjunction with the corresponding upper limit address register controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 39-bit address. the lower 7 bi ts of the upper limit address register are read/write and correspond to address bits a[38:32] of the 39-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fff ffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (that is, prefetchable) from the processor perspective. 2.6.21 capptr?capabilities pointer register the capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. b/d/f/type: 0/1/0/pci address offset: 2c?2fh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore prefetchable memory address limit (pmlimitu) this field corresponds to a[63:32] of the upper limit of the prefetchable memory range that will be passed to pci express- g. b/d/f/type: 0/1/0/pci address offset: 34h reset value: 88h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 88h uncore first capability (capptr1) the first capability in the list is the subsystem id and subsystem vendor id capability. datasheet, volume 2 105 processor configuration registers 2.6.22 intrline?interrupt line register this register contains interrupt line routing information. the device itself does not use this value; rather, it is used by device drivers and operating systems to determine priority and vector information. 2.6.23 intrpin?interrupt pin register this register specifies which interrupt pin this device uses. b/d/f/type: 0/1/0/pci address offset: 3ch reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore interrupt connection (intcon) this field is used to comm unicate interrupt line routing information. bios requirement: post software writes the routing information into this register as it initializes and configures the system. the value indicates to which input of the system interrupt controller th is device's interrupt pin is connected. b/d/f/type: 0/1/0/pci address offset: 3dh reset value: 01h access: rw-o, ro size: 8 bits bit access reset value rst/ pwr description 7:3 ro 00h uncore reserved (rsvd) 2:0 rw-o 1h uncore interrupt pin (intpin) as a multifunction device, the pci express device may specify any intx (x=a,b,c,d) as its interrupt pin. the interrupt pin register indicates which interrupt pin the device (or device function) uses. a value of 1 corresponds to inta# (default) a value of 2 corresponds to intb# a value of 3 corresponds to intc# a value of 4 corresponds to intd# devices (or device functions) that do not use an interrupt pin must put a 0 in this register. the values 05h through ffh are reserved. this register is write once. bios must set this register to select the intx to be used by this root port. processor configuration registers 106 datasheet, volume 2 2.6.24 bctrl?bridge control register this register provides extensions to the pc icmd register that are specific to pci-pci bridges. the bctrl provides additional cont rol for the secondary interface (that is, pci express-g) as well as some bits that affect the overall behavior of the "virtual" host- pci express bridge embedded within the pr ocessor; such as vga compatible address ranges mapping. b/d/f/type: 0/1/0/pci address offset: 3e?3fh reset value: 0000h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 ro 0b uncore discard timer serr# enable (dtserre) not applicable or implem ented. hardwired to 0. 10 ro 0b uncore discard timer status (dtsts) not applicable or implem ented. hardwired to 0. 9ro 0buncore secondary discard timer (sdt) not applicable or implem ented. hardwired to 0. 8ro 0buncore primary discard timer (pdt) not applicable or implem ented. hardwired to 0. 7ro 0buncore fast back-to-back enable (fb2ben) not applicable or implem ented. hardwired to 0. 6rw 0buncore secondary bus reset (sreset) setting this bit triggers a hot reset on the corresponding pci express port. this will force the ltssm to transition to the hot reset state (using recovery) from l0, l0s, or l1 states. 5ro 0buncore master abort mode (mamode) does not apply to pci ex press. hardwired to 0. 4rw 0buncore vga 16-bit decode (vga16d ) enables the pci-to-pci bridge to provide 16-bit decoding of vga i/o address precluding the decoding of alias addresses every 1 kb. this bit only has meaning if bit 3 (vga enable) of this register is also set to 1, enabling vga i/o decoding and forwarding by the bridge. 0 = execute 10-bit address decodes on vga i/o accesses. 1 = execute 16-bit address decodes on vga i/o accesses. 3rw 0buncore vga enable (vgaen) this bit controls the routing of processor initiated transactions targeting vga compatible i/o an d memory address ranges. see the vgaen/mdap table in device 0, offset 97h[0]. datasheet, volume 2 107 processor configuration registers 2.6.25 pm_capid?power manage ment capabilities register 2rw 0buncore isa enable (isaen) needed to exclude legacy resource decode to route isa resources to legacy decode path. modifies the response by the root port to an i/o access issued by the processor that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and io limit registers. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to pci express-g. 1 = the root port will not forward to pci express-g any i/o transactions addressing the last 768 bytes in each 1 kb block, even if the addresses are within the range defined by the iobase and io limit registers. 1rw 0buncore serr enable (serren) 0 = no forwarding of error messages from secondary side to primary side that could result in an serr. 1 = err_cor, err_nonfatal, and err_fatal messages result in serr message when indivi dually enabled by the root control register. 0rw 0buncore parity error response enable (peren) this bit controls whether or not the master data parity error bit in the secondary status register is set when the root port receives across the link (upstream) a read data completion poisoned tlp. 0 = master data parity error bit in secondary status register can not be set. 1 = master data parity error bit in secondary status register can be set. b/d/f/type: 0/1/0/pci address offset: 80?83h reset value: c8039001h access: ro, ro-v size: 32 bits bit access reset value rst/ pwr description 31:27 ro 19h uncore pme support (pmes) this field indicates the power st ates in which this device may indicate pme wake using pci express messaging. d0, d3hot, and d3cold. this device is not requir ed to do anything to support d3hot and d3cold; it simply must report that those states are supported. refer to the pci power management 1.1 specification for encoding explanation and other power management details. 26 ro 0b uncore d2 power state support (d2pss) hardwired to 0 to indicate that the d2 power management state is not supported. 25 ro 0b uncore d1 power state support (d1pss) hardwired to 0 to indicate that the d1 power management state is not supported. b/d/f/type: 0/1/0/pci address offset: 3e?3fh reset value: 0000h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 108 datasheet, volume 2 2.6.26 pm_cs?power management control/status register 24:22 ro 000b uncore auxiliary current (auxc) hardwired to 0 to indicate that there are no 3.3vaux auxiliary current requirements. 21 ro 0b uncore device specific initialization (dsi) hardwired to 0 to indicate that sp ecial initialization of this device is not required before generic class device driver is to use it. 20 ro 0b uncore auxiliary power source (aps) hardwired to 0. 19 ro 0b uncore pme clock (pmeclk) hardwired to 0 to indicate this device does not support pme# generation. 18:16 ro 011b uncore pci pm cap version (pcipmcv) a value of 011b indicates that this function complies with revision 1.2 of the pci power management interface specification . (was previously hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the pci power management interface specification .) 15:8 ro-v 90h uncore pointer to next capability (pnc) this contains a pointer to the next item in the capabilities list. if msich (capl[0] @ 7fh) is 0, then the next item in the capabilities list is the messag e signaled interrupts (msi) capability at 90h. if msich (capl[0] @ 7fh) is 1, then the next item in the capabilities list is the pci express capability at a0h. 7:0 ro 01h uncore capability id (cid) value of 01h identifies this linke d list item (capability structure) as being for pci power management registers. b/d/f/type: 0/1/0/pci address offset: 84?87h reset value: 00000008h access: ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 ro 0b uncore pme status (pmests) this bit indicates that this device does not support pme# generation from d3cold. 14:13 ro 00b uncore data scale (dscale) this field indicates that this device does not support the power management data register. 12:9 ro 0h uncore data select (dsel) this field indicates that this device does not support the power management data register. b/d/f/type: 0/1/0/pci address offset: 80?83h reset value: c8039001h access: ro, ro-v size: 32 bits bit access reset value rst/ pwr description datasheet, volume 2 109 processor configuration registers 8rw 0buncore pme enable (pmee) this bit indicates that this device does not generate pme# assertion from any d-state. 0 = pme# generation not possible from any d state 1 = pme# generation enabled from any d state the setting of this bit has no effect on hardware. see pm_cap[15:11] 7:4 ro 0h reserved (rsvd) 3ro 1buncore no soft reset (nsr) 1 = when set to 1 this bit indicates that the device is transitioning from d3hot to d0 because the power state commands do not perform an in ternal reset. configuration context is preserved. upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits. 0 = when clear the devices do not perform an internal reset upon transitioning from d3hot to d0 using software control of the power state bits. regardless of this bit, the device s that transition from a d3hot to d0 by a system or bus segment reset will return to the device state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2ro 0h reserved (rsvd) 1:0 rw 00b uncore power state (ps) this field indicates the current power state of this device and can be used to set the device into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus; but the data is discarded and no state change occurs. 00 = d0 01 = d1 (not supported in this device.) 10 = d2 (not supported in this device.) 11 = d3 support of d3cold does not require any special action. while in the d3hot state, this device can only act as the target of pci configuration transactions (for power management control). this device also cannot generate interrupts or respond to mmr cycles in the d3 state. the device must return to the d0 state in order to be fully-functional. when the power state is other than d0, the bridge will master abort (that is, not claim) any downstream cycles (with exception of type 0 configuration cycles). consequently, these unclaimed cycles will go down dmi and co me back up as unsupported requests, which the processor logs as master aborts in device 0 pcists[13]. there is no additional hardware fu nctionality requir ed to support these power states. b/d/f/type: 0/1/0/pci address offset: 84?87h reset value: 00000008h access: ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description processor configuration registers 110 datasheet, volume 2 2.6.27 ss_capid?subsystem id and vendor id capabilities register this capability is used to uniquely identify the subsystem where the pci device resides. because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. however, it is necessary because microsoft will test for its presence. 2.6.28 ss?subsystem id and subsystem vendor id register system bios can be used as the mechanism for loading the ssid/svid values. these values must be preserved through power management transitions and a hardware reset. b/d/f/type: 0/1/0/pci address offset: 88?8bh reset value: 0000800dh access: ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:8 ro 80h uncore pointer to next capability (pnc) this field contains a pointer to the next item in the capabilities list which is the pci power management capability. 7:0 ro 0dh uncore capability id (cid) value of 0dh identifies this linked list item (capability structure) as being for ssid/ssvid regist ers in a pci-to-pci bridge. b/d/f/type: 0/1/0/pci address offset: 8c?8fh reset value: 00008086h access: rw-o size: 32 bits bit access reset value rst/ pwr description 31:16 rw-o 0000h uncore subsystem id (ssid) this field identifies the particular subsystem and is assigned by the vendor. 15:0 rw-o 8086h uncore subsystem vendor id (ssvid) this field identifies the manufacturer of the subsystem and is the same as the vendor id which is assigned by the pci special interest group. datasheet, volume 2 111 processor configuration registers 2.6.29 msi_capid?message signal ed interrupts ca pability id register when a device supports msi it can generate an interrupt request to the processor by writing a predefined data item (a me ssage) to a predefined memory address. the reporting of the existence of this ca pability can be disabled by setting msich (capl[0] @ 7fh). in that case walking this linked list will skip this capability and instead go directly from the pci pm capability to the pci express capability. b/d/f/type: 0/1/0/pci address offset: 90?91h reset value: a005h access: ro size: 16 bits bit access reset value rst/ pwr description 15:8 ro a0h uncore pointer to next capability (pnc) this field contains a pointer to the next item in the capabilities list which is the pci express capability. 7:0 ro 05h uncore capability id (cid) value of 05h identifies this linked list item (capability structure) as being for msi registers. processor configuration registers 112 datasheet, volume 2 2.6.30 mc?message control register system software can modify bits in this register, but the device is prohibited from doing so. if the device writes the same message multiple times, only one of those messages is ensured to be serviced. if all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. b/d/f/type: 0/1/0/pci address offset: 92?93h reset value: 0000h access: rw, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:8 ro 0h reserved (rsvd) 7ro 0buncore 64-bit address capable (b64ac) hardwired to 0 to indicate that the function does not implement the upper 32 bits of the message address register and is incapable of generating a 64-bit memory address. 6:4 rw 000b uncore multiple message enable (mme) system software programs this field to indicate the actual number of messages allocated to this device. this number will be equal to or less than the number actually requested. the encoding is the same as for the mmc field below. 3:1 ro 000b uncore multiple message capable (mmc) system software reads this field to determine the number of messages being requested by this device. 000 = 1 message requested all of the following are reserv ed in this implementation: 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = reserved 111 = reserved 0rw 0buncore msi enable (msien) this bit controls the ability of this device to generate msis. 0 = msi will not be generated. 1 = msi will be generated when we receive pme messages. inta will not be generated and inta status (pcists1[3]) will not be set. datasheet, volume 2 113 processor configuration registers 2.6.31 ma?message address register 2.6.32 md?message data register b/d/f/type: 0/1/0/pci address offset: 94?97h reset value: 00000000h access: rw, ro size: 32 bits bit access reset value rst/ pwr description 31:2 rw 00000000h uncore message address (ma) used by system software to assign an msi address to the device. the device handles an msi by writing the padded contents of the md register to this address. 1:0 ro 00b uncore force dword align (fdwa) hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. b/d/f/type: 0/1/0/pci address offset: 98?99h reset value: 0000h access: rw size: 16 bits bit access reset value rst/ pwr description 15:0 rw 0000h uncore message data (md) base message data pattern assigned by system software and used to handle an msi from the device. when the device must generate an interrupt request, it writes a 32-bit value to the memory addres s specified in the ma register. the upper 16 bits are always set to 0. the lower 16 bits are supplied by this register. processor configuration registers 114 datasheet, volume 2 2.6.33 peg_capl?pci express- g capability list register this register enumerates the pci express* capability structure. 2.6.34 peg_cap?pci expres s-g capabilities register this register indicates pci express* device capabilities. b/d/f/type: 0/1/0/pci address offset: a0?a1h reset value: 0010h access: ro size: 16 bits bit access reset value rst/ pwr description 15:8 ro 00h uncore pointer to next capability (pnc) this value terminates the capabi lities list. the virtual channel capability and any other pci expre ss specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within pci express extended configuration space. 7:0 ro 10h uncore capability id (cid) this field identifies this linked list item (capability structure) as being for pci express registers. b/d/f/type: 0/1/0/pci address offset: a2?a3h reset value: 0142h access: ro, rw-o size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:14 ro 0h reserved (rsvd) 13:9 ro 00h uncore interrupt message number (imn) not applicable or implemented. hardwired to 0. 8rw-o 1b uncore slot implemented (si) 0 = the pci express link associated with this port is connected to an integrated component or is disabled. 1 = the pci express link associated with this port is connected to a slot. bios requirement: this field must be initialized appropriately if a slot connection is not implemented. 7:4 ro 4h uncore device/port type (dpt) hardwired to 4h to indicate root port of pci express root complex. 3:0 ro 2h uncore pci express capability version (pciecv) hardwired to 2h to indicate compliance to the pci express capabilities register expansion ecn. datasheet, volume 2 115 processor configuration registers 2.6.35 dcap?device ca pabilities register this register indicates pci express* device capabilities. b/d/f/type: 0/1/0/pci address offset: a4?a7h reset value: 00008000h access: ro, rw-o size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 ro 1b uncore role based error reporting (rber) this bit indicates that this devi ce implements the functionality defined in the error reporting ecn as required by the pci express 1.1 specification. 14:6 ro 0h reserved (rsvd) 5ro 0buncore extended tag field supported (etfs) hardwired to indicate support for 5-bit tags as a requestor. 4:3 ro 00b uncore phantom functions supported (pfs) not applicable or imple mented. hardwired to 0. 2:0 rw-o 000b uncore max payload size (mps) default indicates 128b maximum supported payload for transaction layer packets (tlp). processor configuration registers 116 datasheet, volume 2 2.6.36 dctl?device control register this register provides control for pci express* device specific capabilities. the error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. th e reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclusively by root port command register. b/d/f/type: 0/1/0/pci address offset: a8?a9h reset value: 0020h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 ro 0h reserved (rsvd) 14:12 ro 000b uncore reserved for max read request size (mrrs) 11 ro 0b uncore reserved for enable no snoop (nse) 10:5 ro 0h reserved (rsvd) 4ro 0buncore reserved for enable relaxed ordering (roe) 3rw 0buncore unsupported request reporting enable (urre) when set, this bit allows sign aling err_nonfatal, err_fatal, or err_corr to the root control register when detecting an unmasked unsupported request (ur). an err_corr is signaled when an unmasked advisory non-fatal ur is received. an err_fatal or err_nonfatal is sent to the root control register when an uncorrectable non-advisory ur is received with the severity bit set in the uncorrectable error severity register. 2rw 0buncore fatal error reporting enable (fere) when set, this bit enables sign aling of err_fatal to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. 1rw 0buncore non-fatal error reporting enable (nere) when set, this bit enables sign aling of err_nonfatal to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. 0rw 0buncore correctable error reporting enable (cere) when set, this bit enables sign aling of err_corr to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. datasheet, volume 2 117 processor configuration registers 2.6.37 dsts?device status register this register reflects status corresponding to controls in the device control register. the error reporting bits are in reference to errors detected by this device, not errors messages received across the link. b/d/f/type: 0/1/0/pci address offset: aa?abh reset value: 0000h access: rw1c, ro size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:6 ro 0h reserved (rsvd) 5ro 0buncore transactions pending (tp ) 0 = all pending transactions (i ncluding completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used traffic classes). not applicable or impleme nted. hardwired to 0. 4ro 0h reserved (rsvd) 3rw1c 0b uncore unsupported request detected (urd) this bit indicates that the function received an unsupported request. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. 2rw1c 0b uncore fatal error detected (fed) this bit indicates status of fatal errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. 1rw1c 0b uncore non-fatal error detected (nfed) this bit indicates status of nonfatal errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. 0rw1c 0b uncore correctable error detected (ced) this bit indicates status of correctable errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. processor configuration registers 118 datasheet, volume 2 2.6.38 lcap?link capabilities register b/d/f/type: 0/1/0/pci address offset: ac?afh reset value: 0261cd03h access: ro, ro-v, rw-o, rw-ov size: 32 bits bit access reset value rst/ pwr description 31:24 ro 02h uncore port number (pn) this field indicates the pci express port number for the given pci express link. matches the value in element self description[31:24]. the value if this field differs between root ports 2h = device 1 function 0 3h = device 1 function 1 4h = device 1 function 2 5h = device 6 function 0 23 ro 0h reserved (rsvd) 22 ro 1b uncore aspm optionality compliance (aoc) this bit must be set to 1b in all functions. components implemented against certain earlier versions of this specification will have this bit set to 0b. softwa re is permitted to use the value of this bit to help determine wh ether to enable aspm or whether to run aspm compliance tests. 21 ro 1b uncore link bandwidth notification capability (lbnc) a value of 1b indicates support for the link bandwidth notification status and interrup t mechanisms. this capability is required for all root ports and switch downstream ports supporting links wider than x1 and/or multiple link speeds. this field is not applicable and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. devices that do not implement th e link bandwidth notification capability must hardwire this bit to 0b. 20 ro 0b uncore data link layer link active reporting capable (dlllarc) for a downstream port, this bit must be set to 1b if the component supports the optional capability of reporting the dl_active state of the data link control and management state machine. for a hot-plug capable downstream port (as indicated by the hot-plug capable field of the slot capabilities register), this bit must be set to 1b. for upstream ports and components that do not support this optional capability, this bit must be hardwired to 0b. note: pci express* hot-plug is not supported on the processor. 19 ro 0b uncore surprise down error reporting capable (sderc) for a downstream port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a surprise down error condition. for upstream ports and components that do not support this optional capability, this bit must be hardwired to 0b. datasheet, volume 2 119 processor configuration registers 18 ro 0b uncore clock power management (cpm) a value of 1b in this bit indicates that the component tolerates the removal of any reference clock( s) when the link is in the l1 and l2/3 ready link states. a value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these link states. this capability is applicable onl y in form factors that support "clock request" (clkreq#) capability. for a multi-function device, each function indicates its capability independently. power management configuration software must only permit reference clock remo val if all functions of the multifunction device indica te a 1b in this bit. 17:15 ro 0h reserved (rsvd) 14:12 ro-v 100b uncore l0s exit latency (l0selat) this field indicates the length of time this port requires to complete the transition from l0s to l0. 000 = less than 64 ns 001 = 64 ns to less than 128 ns 010 = 128 ns to less than 256 ns 011 = 256 ns to less than 512 ns 100 = 512 ns to less than 1 us 101 = 1 us to less than 2 us 110 = 2 us?4 us 111 = more than 4 us the actual value of this field depends on the common clock configuration bit (lctl[6]) and the common and non-common clock l0s exit latency values in l0slat (offset 22ch) 11:10 rw-o 11b uncore active state link pm support (aslpms) root port supports aspm l0s and l1. 9:0 ro 0h reserved (rsvd) b/d/f/type: 0/1/0/pci address offset: ac?afh reset value: 0261cd03h access: ro, ro-v, rw-o, rw-ov size: 32 bits bit access reset value rst/ pwr description processor configuration registers 120 datasheet, volume 2 2.6.39 lctl?link control register this register allows control of pci express* link. b/d/f/type: 0/1/0/pci address offset: b0?b1h reset value: 0000h access: rw, ro, rw-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 rw 0b uncore link autonomous bandwidth interrupt enable (labie) when set, this bit enables the generation of an interrupt to indicate that the link autonomous bandwidth status bit has been set. this bit is not applicab le and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. devices that do not implement th e link bandwidth notification capability must hardwire this bit to 0b. 10 rw 0b uncore link bandwidth management interrupt enable (lbmie) when set, this bit enables the generation of an interrupt to indicate that the link bandwidth management status bit has been set. this bit is not applicab le and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. 9rw 0buncore hardware autonomous width disable (hawd) when set, this bit disables hardware from changing the link width for reasons other than attempting to correct unreliable link operation by reducing link width devices that do not implemen t the ability autonomously to change link width are permitted to hardwire this bit to 0b. 8ro 0buncore enable clock power management (ecpm) applicable only for form factors that support a "clock request" (clkreq#) mechanism, this en able functions as follows 0 = clock power management is disabled and device must hold clkreq# signal low 1 = when this bit is set to 1 the device is permitted to use clkreq# signal to power manage link clock according to protocol defined in appropriate form factor specification. reset value of this field is 0b. components that do not support clock power management (as indicated by a 0b value in the clock power management bit of the link capabilities register) must hardwire this bit to 0b. 7rw 0buncore extended synch (es) 0 = standard fast training sequence (fts). 1 = forces the transmission of additional ordered sets when exiting the l0s state and when in the recovery state. this mode provides external devices (such as, logic analyzers) monitoring the link time to achi eve bit and symbol lock before the link enters l0 and resumes communication. this is a test mode only and may cause other undesired side effects such as buffer overflows or underruns. datasheet, volume 2 121 processor configuration registers 6rw 0buncore common clock configuration (ccc) 0 = indicates that this compon ent and the component at the opposite end of this link are operating with asynchronous reference clock. 1 = indicates that this compon ent and the component at the opposite end of this link are operating with a distributed common reference clock. the state of this bit affects the l0s exit latency reported in lcap[14:12] and the n_fts value advertised during link training. see l0slat at offset 22ch. 5rw-v 0b uncore retrain link (rl) 0 = normal operation. 1 = full link retraining is initiate d by directing the physical layer ltssm from l0, l0s, or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). 4ro 0h link disable (ld) 0 = normal operation 1 = link is disabled. forces the ltssm to transition to the disabled state (using recovery) from l0, l0s, or l1 states. link retraining happens automatically on the 0 to1 transtion, just like when coming out of reset. writes to this bit are immediately reflected in the value read from the bit, regardless of actual link state. after clearing this bit, software must honor timing requirements defined in the pcie specification, section 6.6.1, with respect to the first configuration read following a conventional reset. 3ro 0buncore read completion boundary (rcb) hardwired to 0 to indicate 64 byte. 2ro 0h reserved (rsvd) 1:0 rw 00b uncore active state pm (aspm) this field controls the level of aspm (active state power management) supported on the given pci express link. b/d/f/type: 0/1/0/pci address offset: b0?b1h reset value: 0000h access: rw, ro, rw-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 122 datasheet, volume 2 2.6.40 lsts?link status register the register indicates pci express* link status. b/d/f/type: 0/1/0/pci address offset: b2?b3h reset value: 1001h access: rw1c, ro-v, ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 rw1c 0b uncore link autonomous bandwidth status (labws) this bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through dl_down status, for reasons other than to attempt to correct unreliable link operation. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change. 14 rw1c 0b uncore link bandwidth management status (lbwms) this bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through dl_down status: ? a link retraining initiated by a write of 1b to the retrain link bit has completed. note: this bit is set following any write of 1b to the retrain link bit, including when the link is in the process of retraining for some other reason. ? hardware has autonomously changed link speed or width to attempt to correct unreliable link operation, either through an ltssm time-out or a higher level process. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change. 13 ro-v 0b uncore data link layer link active (optional) (dllla) this bit indicates the status of the data link control and management state machine. it returns a 1b to indicate the dl_active state, 0b otherwise. this bit must be implemented if the corresponding data link layer active capability bit is implemented. otherwise, this bit must be hardwired to 0b. 12 ro 1b uncore slot clock configuration (scc) 0 = the device uses an independent clock irrespective of the presence of a reference on the connector. 1 = the device uses the same ph ysical reference clock that the platform provides on the connector. 11 ro-v 0b uncore link training (ltrn) when set, this bit indicates that the physical layer ltssm is in the configuration or recovery state, or that 1b was written to the retrain link bit but link training has not yet begun. hardware clears this bit when the ltssm exits the configuration/recovery state once link training is complete. datasheet, volume 2 123 processor configuration registers 2.6.41 slotcap?slot capabilities register note: pci express* hot-plug is not supported on the processor. 10 ro 0h reserved (rsvd) 9:4 ro-v 00h uncore negotiated link width (nlw) this field indicates negotiated link width. this field is valid only when the link is in the l0, l0s, or l1 states (after link width negotiation is successfully completed). 00h = reserved 01h = x1 02h = x2 04h = x4 08h = x8 10h = x16 all other encodings are reserved. 3:0 ro 0h current link speed (cls) this field indicates the negotiated link speed of the given pci express link. the encoding is the binary valu e of the bit location in the supported link speeds vector (in the link capabilities 2 register) that corresponds to the current link speed. for example, a value of 0010b in this field indicates that the current link speed is that corres ponding to bit 2 in the supported link speeds vector, which is 5.0 gt/s. all other encodings are reserved. the value in this field is undefined when the link is not up. b/d/f/type: 0/1/0/pci address offset: b4?b7h reset value: 00040000h access: rw-o, ro size: 32 bits bit access reset value rst/ pwr description 31:19 rw-o 0000h uncore physical slot number (psn) this field indicates the physical slot number attached to this port. bios requirement: this field must be initialized by bios to a value that assigns a slot number that is globally unique within the chassis. 18 ro 1b uncore no command completed support (nccs) when set to 1b, this bit indicates that this slot does not generate software notification when an issued command is completed by the hot-plug controller. this bit is only permitted to be set to 1b if the hot-plug capable port is able to accept wr ites to all fields of the slot control register without delay between successive writes. 17 ro 0b uncore reserved for electromechanical interlock present (eip) when set to 1b, this bit indicates that an electromechanical interlock is implemented on the chassis for this slot. b/d/f/type: 0/1/0/pci address offset: b2?b3h reset value: 1001h access: rw1c, ro-v, ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 124 datasheet, volume 2 16:15 rw-o 00b uncore slot power limit scale (spls) this field specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x if this field is written, the link sends a set_slot_power_limit message. 14:7 rw-o 00h uncore slot power limit value (splv) in combination with the slot po wer limit scale value, specifies the upper limit on power supplied by slot. power limit (in watts) is calculated by multiplying the va lue in this field by the value in the slot power limit scale field. if this field is written, the link sends a set_slot_power_limit message. 6ro 0buncore reserved for hot-plug capable (hpc) when set to 1b, this bit indicates that this slot is capable of supporting hot-plug operations. 5ro 0buncore reserved for hot-plug surprise (hps) when set to 1b, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. this is a form factor specific capability. this bit is an indication to the operating syst em to allow for such removal without impacting continued software operation. 4ro 0buncore reserved for power indicator present (pip) when set to 1b, this bit indicates that a power indicator is electrically controlled by the chassis for this slot. 3ro 0buncore reserved for attention indicator present (aip) when set to 1b, this bit indicate s that an attention indicator is electrically controlled by the chassis. 2ro 0buncore reserved for mrl sensor present (msp) when set to 1b, this bit indicates that an mrl sensor is implemented on the chassis for this slot. 1ro 0buncore reserved for power controller present (pcp) when set to 1b, this bit indicates that a software programmable power controller is implemented fo r this slot/adapter (depending on form factor). 0ro 0buncore reserved for attention button present (abp) when set to 1b, this bit indicates that an attention button for this slot is electrically controlled by the chassis. b/d/f/type: 0/1/0/pci address offset: b4?b7h reset value: 00040000h access: rw-o, ro size: 32 bits bit access reset value rst/ pwr description datasheet, volume 2 125 processor configuration registers 2.6.42 slotctl?slot control register note: pci express* hot-plug is not supported on the processor. b/d/f/type: 0/1/0/pci address offset: b8?b9h reset value: 0000h access: ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:13 ro 0h reserved (rsvd) 12 ro 0b uncore reserved for data link layer state changed enable (dllsce) if the data link layer link active capability is implemented, when set to 1b, this field enables software notification when data link layer link active field is changed. if the data link layer link acti ve capability is not implemented, this bit is permitted to be read-only with a value of 0b. 11 ro 0b uncore reserved for electromechanical interlock control (eic) if an electromechanical interlock is implemented, a write of 1b to this field causes the state of the interlock to toggle. a write of 0b to this field has no effect. a read to this register always returns a 0. 10 ro 0b uncore reserved for power controller control (pcc) if a power controller is implemented, this field when written sets the power state of the slot per the defined encodings. reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case th e read value is undefined. depending on the form factor, the power is turned on/off either to the slot or within the adap ter. in some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the power controller control setting. the defined encodings are: 0 = power on 1 = power off if the power controller implemented field in the slot capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined. 9:8 ro 00b uncore reserved power indicator control (pic) if a power indicator is implemente d, writes to this field set the power indicator to the written state. reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the prev ious command to complete in which case the read value is undefined. 00 = reserved 01 = on 10 = blink 11 = off if the power indicator present bit in the slot capabilities register is 0b, this field is permitted to be read-only with a value of 00b. processor configuration registers 126 datasheet, volume 2 7:6 ro 00b uncore reserved for attention indicator control (aic) if an attention indicator is implem ented, writes to this field set the attention indicator to the written state. reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. if the indicator is electrically controlled by chassis, the indicator is controlled directly by the downstream port through implementation specific mechanisms. 00 = reserved 01 = on 10 = blink 11 = off if the attention indicator present bit in the slot capabilities register is 0b, this field is permitted to be read only with a value of 00b. 5ro 0buncore reserved for hot-plug interrupt enable (hpie) when set to 1b, this bit enables generation of an interrupt on enabled hot-plug events reset value of this field is 0b. if the hot-plug capable field in the slot capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 4ro 0buncore reserved for command completed interrupt enable (cci) if command completed notification is supported (as indicated by no command completed support field of slot capabilities register), when set to 1b, this bit enables software notification when a hot-plug command is completed by the hot-plug controller. if command completed notificatio n is not supported, this bit must be hardwired to 0b. 3ro 0buncore presence detect changed enable (pdce) when set to 1b, this bit enables software notification on a presence detect changed event. 2ro 0buncore reserved for mrl sensor changed enable (msce) when set to 1b, this bit enables software notification on a mrl sensor changed event. if the mrl sensor present field in the slot capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 1ro 0buncore reserved for power fault detected enable (pfde) when set to 1b, this bit enables software notification on a power fault event. if power fault detection is not supp orted, this bit is permitted to be read-only with a value of 0b 0ro 0buncore reserved for attention butt on pressed enable (abpe) when set to 1b, this bit enables software notification on an attention button pressed event. b/d/f/type: 0/1/0/pci address offset: b8?b9h reset value: 0000h access: ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description datasheet, volume 2 127 processor configuration registers 2.6.43 slotsts?slot status register this is a pci express* slot related register. b/d/f/type: 0/1/0/pci address offset: ba?bbh reset value: 0000h access: ro, rw1c, ro-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:9 ro 0h reserved (rsvd) 8ro 0buncore reserved for data link layer state changed (dllsc) this bit is set when the value reported in the data link layer link active field of the link status register is changed. in response to a data link layer state changed event, software must read the data link layer link active field of the link status register to determine if the link is active befo re initiating configuration cycles to the hot plugged device. 7ro 0buncore reserved for electromechanical interlock status (eis) if an electromechanical interlock is implemented, this bit indicates the current status of the electromechanical interlock. 0 = electromechanical interlock disengaged 1 = electromechanical interlock engaged 6ro-v 0b uncore presence detect state (pds) in band presence detect state: 0 = slot empty 1 = card present in slot this bit indicates the presence of an adapter in the slot, reflected by the logical "or" of the physic al layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism. 0 = slot empty 1 = card present in slot this register must be implemented on all downstream ports that implement slots. for downstream ports not connected to slots (where the slot implemented bit of the pci express capabilities register is 0b), this bit must return 1b. 5ro 0buncore reserved for mrl sensor state (mss) this register reports the status of the mrl sensor if it is implemented. 0 = mrl closed 1 = mrl open 4ro 0buncore reserved for command completed (cc) if command completed notification is supported (as indicated by no command completed support field of slot capabilities register), this bit is set when a hot-plug command has completed and the hot-plug controller is ready to accept a subsequent command. the command completed status bit is set as an indication to host software that the hot-plug controller has processed the previous command and is ready to receive the next command; it provides no assurance that the action corresponding to the command is complete. if command completed notification is not supported, this bit must be hardwired to 0b. processor configuration registers 128 datasheet, volume 2 3rw1c 0b uncore presence detect changed (pdc) a pulse indication that the inba nd presence detect state has changed. this bit is set when the value reported in presence detect state is changed. 2ro 0buncore reserved for mrl sensor changed (msc) if an mrl sensor is implemented, this bit is set when a mrl sensor state change is detected. if an mrl sensor is not implemented, this bit must not be set. 1ro 0buncore reserved for power fault detected (pfd) if a power controller that supp orts power fault detection is implemented, this bit is set when the power controller detects a power fault at this slot. dependin g on hardware capability, it is possible that a power fault can be detected at any time, independent of the power controller control setting or the occupancy of the slot. if power fault detection is not supported, this bit must not be set. 0ro 0buncore reserved for attention button pressed (abp) if an attention button is implemen ted, this bit is set when the attention button is pressed. if an attention button is not supported, this bit must not be set. b/d/f/type: 0/1/0/pci address offset: ba?bbh reset value: 0000h access: ro, rw1c, ro-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description datasheet, volume 2 129 processor configuration registers 2.6.44 rctl?root control register this register allows control of pci expre ss* root complex specific parameters. the system error control bits in this regist er determine if corresponding serrs are generated when our device detects an error (reported in this device's device status register) or when an error message is received across the link. reporting of serr as controlled by these bits takes precedence over the serr enable in the pci command register. b/d/f/type: 0/1/0/pci address offset: bc?bdh reset value: 0000h access: ro, rw size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:5 ro 0h reserved (rsvd) 4ro 0buncore reserved for crs software visibility enable (csve) this bit, when set, enables the ro ot port to return configuration request retry status (crs) completion status to software. root ports that do not implemen t this capability must hardwire this bit to 0b. 3rw 0buncore pme interrupt enable (pmeie) 0 = no interrupts are generated as a result of receiving pme messages. 1 = enables interrupt generation upon receipt of a pme message as reflected in the pme status bit of the root status register. a pme interrupt is also generated if the pme status bit of the root status register is set when this bit is set from a cleared state. if the bit change from 1 to 0 and interrupt is pending than interrupt is deasserted 2rw 0buncore system error on fatal error enable (sefee) controls the root complex's response to fatal errors. 0 = no serr generated on receipt of fatal error. 1 = indicates that an serr should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 1rw 0buncore system error on non-fatal uncorrectable error enable (senfuee) controls the root complex's response to non-fatal errors. 0 = no serr generated on receipt of non-fatal error. 1 = indicates that an serr should be generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 0rw 0buncore system error on correctable error enable (secee) controls the root complex's response to correctable errors. 0 = no serr generated on receipt of correctable error. 1 = indicates that an serr should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. processor configuration registers 130 datasheet, volume 2 2.6.45 rsts?root status register this register provides information about pci express* root complex specific parameters. b/d/f/type: 0/1/0/pci address offset: c0?c3h reset value: 00000000h access: ro, rw1c, ro-v size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:18 ro 0h reserved (rsvd) 17 ro 0b uncore pme pending (pmep) this bit indicates that anothe r pme is pendin g when the pme status bit is set. when the pme st atus bit is cleared by software, the pme is delivered by hardware by setting the pme status bit again and updating the requestor id appropriately. the pme pending bit is cleared by hardware if no more pmes are pending. 16 rw1c 0b uncore pme status (pmes) this bit indicates that pme was asserted by the requestor id indicated in the pme requestor id field. subsequent pmes are kept pending until the status register is cleared by writing a 1 to this field. an interrupt is asserted if pm eie is asserted and pmes is changing from 0 to 1. an interrupt is deasserted if pmeie is asserted and pmes is changing from 1 to 0. an assert_pmegpe is sent upstre am if pmegpee in peg legacy control register (peglc) is asserted and pmes is changing from 0 to 1. a deassert_pmegpe is sent upstre am if pmegpee in peg legacy control register (peglc) is asserted and pmes is changing from 1 to 0 an interrupt is deasserted if pmeie is asserted and pmes is changing from 1 to 0. 15:0 ro-v 0000h uncore pme requestor id (pmerid) this field indicates the pci requestor id of the last pme requestor. datasheet, volume 2 131 processor configuration registers 2.6.46 dcap2?device ca pabilities 2 register b/d/f/type: 0/1/0/pci address offset: c4?c7h reset value: 00000800h access: ro, rw-o size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:12 ro 0h reserved (rsvd) 11 ro 1b uncore latency tolerance and bw reporting mechanism supported (ltrs) a value of 1b indicates support fo r the optional latency tolerance & bandwidth requirement reporting (ltbwr) mechanism capability. root ports, switches and endpoints are permitted to implement this capability. for switches that implement ltbwr, this bit must be set only at the upstream port. for a multi-function device, each function must report the same value for this bit. for bridges, downstream ports, and components that do not implement this capability, this bit must be hardwired to 0b. 10:6 ro 0h reserved (rsvd) 5rw-o 0b uncore ari forwarding supported (arifs) applicable only to switch downstre am ports and root ports; must be 0b for other function types. th is bit must be set to 1b if a switch downstream port or root port supports this optional capability. 4ro 0buncore completion time-out disabled supported (ctods) a value of 1b indicates support for the completion timeout disable mechanism. the completion timeout disable mechanism is required for endpoints that issue requests on their own behalf and pci express to pci/pci-x bridges that take ownership of requests issued on pci express. this mechanism is optional for root ports. the root port does not support completion timeout disable. 3:0 ro 0000b uncore completion timer ranges supported (ctor) device function support for the optional completion timeout programmability mechanism. th is mechanism allows system software to modify the completion timeout value. this field is applicable only to root ports, endpoints that issue requests on their own behalf, and pci express to pci/pci-x bridges that take ownership of requests issued on pci express. for all other functions this field is reserved and must be hardwired to 0000b. 0000b = completion timeout programming not supported ? the function must implement a time-out value in the range 50 s to 50 ms. processor configuration registers 132 datasheet, volume 2 2.6.47 dctl2?device control 2 register b/d/f/type: 0/1/0/pci address offset: c8?c9h reset value: 0000h access: rw-v, rw size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 rw-v 0b uncore latency tolerance and bw reporting mechanism enable (ltren) when set to 1b, this bit enables the latency tolerance & bandwidth requirement reporting (ltbwr) mechanism. this bit is required for all f unctions that support the ltbwr capability. for a multi-function device associated with an upstream port of a device that implements ltbwr, the bit in function 0 is of type rw, and only function 0 controls the component?s link behavior. in all other functions of that device, this bit is of type rsvdp. components that do not implement ltbwr are permitted to hardwire this bit to 0b. reset value of this bit is 0b. this bit is cleared when the port goes to dl_down state. hardware ignores the value of this bit. 10:6 ro 0h reserved (rsvd) 5rw 0buncore ari forward enable (arifen) when set, the downstream port disables its traditional device number field being 0 enforcement when turning a type 1 configuration request into a type 0 configuration request, permitting access to extended functions in an ari device immediately below the port. reset value of this bit is 0b. it must be hardwired to 0b if the ari forwarding supported bit is 0b. 4:0 ro 0h reserved (rsvd) datasheet, volume 2 133 processor configuration registers 2.6.48 lcap2?link capabilities 2 register 2.6.49 lctl2?link control 2 register b/d/f/type: 0/1/0/mmr address offset: cc?cfh reset value: 0000000eh access: ro-v size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:1 ro-v 07h uncore supported link speeds vector (slsv) this field indicates the supported link speed(s) of the associated port. for each bit, a value of 1b indicates that the corresponding link speed is supported; otherwise, the link speed is not supported. bit definitions are: bit 1 = 2.5 gt/s bit 2 = 5.0 gt/s bit 3 = 8.0 gt/s bits 7:4 = reserved multi-function devices associated with an upstream port must report the same value in this field for all functions. dmi does not support this control register since it is gen3 register. 0ro 0h reserved (rsvd) b/d/f/type: 0/1/0/pci address offset: d0?d1h reset value: 0003h access: rws, rws-v size: 16 bits bit access reset value rst/ pwr description 15:11 ro 0h reserved (rsvd) 10 rws 0b powergood enter modified compliance (entermodcompliance) when this bit is set to 1b, the device transmits modified compliance pattern if the lt ssm enters polling.compliance state. components that support onl y the 2.5 gt/s speed are permitted to hardwire this bit to 0b. reset value of this field is 0b. 9:7 ro 0h reserved (rsvd) processor configuration registers 134 datasheet, volume 2 6rws 0bpowergood selectable de-emphasis (selectabledeemphasis) when the link is operating at 5 gt/s speed, selects the level of de-emphasis. encodings: 1 = -3.5 db 0 = -6 db reset value is implementation sp ecific, unless a specific value is required for a selected form factor or platform. when the link is operating at 2.5 gt/s speed, the setting of this bit has no effect. components that support only the 2.5 gt/s speed are permitted to hardwire this bit to 0b. 5:4 ro 0h reserved (rsvd) 3:0 rws 3h powergood target link speed (tls) for downstream ports, this fiel d sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. defined encodings are: 0001b = 2.5 gb/s target link speed 0010b = 5 gb/s target link speed 0011b = 8 gb/s target link speed all other encodings are reserved. if a value is written to this fiel d that does not correspond to a speed included in the supported link speeds field, the result is undefined. the reset value of this field is the highest link speed supported by the component (as reported in the supported link speeds field of the link capabilities register) unless the corresponding platform / form factor requires a different reset value. for both upstream and downstream ports, this field is used to set the target compliance mode speed when software is using the enter compliance bit to fo rce a link into compliance mode. b/d/f/type: 0/1/0/pci address offset: d0?d1h reset value: 0003h access: rws, rws-v size: 16 bits bit access reset value rst/ pwr description datasheet, volume 2 135 processor configuration registers 2.6.50 lsts2?link status 2 register b/d/f/type: 0/1/0/pci address offset: d2?d3h reset value: 0000h access: ro-v, rw1c size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:6 ro 0h reserved (rsvd) 5rw1c 0b uncore link equalization request (lnkeqreq) t his bit is set by hardware to request the link equalization process to be performed on the link . refer to pcie specification, sections 4.2.3 and 4. 2.6.4.2 for details. the reset value of this bit is 0b. 4ro-v 0b uncore equalization phase 3 successful (eqph3succ) when set to 1b, this bit indicates that phase 3 of the transmitter equalization procedure has successf ully completed. details of the transmitter equalizatio n process and when this bit needs to be set to 1b is provided in pcie specification, section 4.2.6.4.2. the reset value of this bit is 0b. 3ro-v 0b uncore equalization phase 2 successful (eqph2succ) when set to 1b, this bit indicates that phase 2 of the transmitter equalization procedure has successf ully completed. details of the transmitter equalizatio n process and when this bit needs to be set to 1b is provided in pcie specification section 4.2.6.4.2. the reset value of this bit is 0b. 2ro-v 0b uncore equalization phase 1 successful (eqph1succ) when set to 1b, this bit indicates that phase 1 of the transmitter equalization procedure has successf ully completed. details of the transmitter equalizatio n process and when this bit needs to be set to 1b is provided in pcie specification section 4.2.6.4.2. the reset value of this bit is 0b. 1ro-v 0b uncore equalization comple te (eqcomplete) when set to 1b, this bit in dicates that the transmitter equalization procedure has completed. details of the transmitter equalization process and when this bit needs to be set to 1b is provided in pcie specification section 4.2.6.4.2. the reset value of this bit is 0b. 0ro-v 0b uncore current de-emphasis level (curdelvl) when the link is operating at 5 gt/s speed, this reflects the level of de-emphasis. 1 = -3.5 db 0 = -6 db when the link is operating at 2. 5 gt/s speed, this bit is 0b. processor configuration registers 136 datasheet, volume 2 2.7 pci device 1 function 0 extended configuration registers table 2-10. pci device 1 function 0 exte nded configuration register address map address offset register symbol register name reset value access 0?103h rsvd reserved 0h ro 104?107h pvccap1 port vc capability register 1 00000000h ro 108?10bh pvccap2 port vc capability register 2 00000000h ro 10c?10dh pvcctl port vc control 0000h rw, ro 10e?10fh rsvd reserved 0h ro 110?113h vc0rcap vc0 resource capability 00000001h ro 114?117h vc0rctl vc0 resource control 800000ffh ro, rw 118?119h rsvd reserved 0h ro 11a?11bh vc0rsts vc0 resource status 0002h ro-v 11c?207h rsvd reserved 0h ro 208?20bh peg_tc pci express completion time-out 00010005h rw 20c?d9fh rsvd reserved 02000100h ro, rw-o da0?da3h eqctl0_1 lane 0/1 equalization control register 07080708h rw da4?da7h eqctl2_3 lane 2/3 equalization control register 07080708h rw da8?dabh eqctl4_5 lane 4/5 equalization control register 07080708h rw dac?dafh eqctl6_7 lane 6/7 equalization control register 07080708h rw db0?db3h eqctl8_9 lane 8/9 equalization control register 07080708h rw db4?db7h eqctl10_11 lane 10/11 equalization control register 07080708h rw db8?dbbh eqctl12_13 lane 12/13 equalization control register 07080708h rw dbc?dbfh eqctl14_15 lane 14/15 equalization control register 07080708h rw dc0?dd7h rsvd reserved 0h ro dd8?ddbh eqcfg equalization configuration register f9404400h rw datasheet, volume 2 137 processor configuration registers 2.7.1 pvccap1?port vc capability register 1 this register describes the configuration of pci express* virtual channels associated with this port. 2.7.2 pvccap2?port vc capability register 2 this register describes the configuration of pci express* virtual channels associated with this port. b/d/f/type: 0/1/0/mmr address offset: 104?107h reset value: 00000000h access: ro size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:7 ro 0h reserved (rsvd) 6:4 ro 000b uncore low priority extended vc count (lpevcc) this field indicates the number of (extended) virtual channels in addition to the default vc belongin g to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 3ro 0h reserved (rsvd) 2:0 ro 000b uncore extended vc count (evcc) this field indicates the number of (extended) virtual channels in addition to the default vc supported by the device. b/d/f/type: 0/1/0/mmr address offset: 108?10bh reset value: 00000000h access: ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 ro 00h uncore vc arbitration table offset (vcato) this field indicates the location of the vc arbitration table. this field contains the zero-based o ffset of the table in dqwords (16 bytes) from the base address of the virtual channel capability structure. a value of 0 indicates that the table is not present (due to fixed vc priority). 23:8 ro 0h reserved (rsvd) 7:0 ro 00h uncore reserved for vc arbitration capability (vcac) processor configuration registers 138 datasheet, volume 2 2.7.3 pvcctl?port vc control register b/d/f/type: 0/1/0/mmr address offset: 10c?10dh reset value: 0000h access: rw, ro size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:4 ro 0h reserved (rsvd) 3:1 rw 000b uncore vc arbitration select (vcas) this field will be programmed by software to the only possible value as indicated in the vc ar bitration capability field. since there is no other vc supported than the default, this field is reserved. 0ro 0buncore reserved for load vc arbitration table (vcarb) used for software to update th e vc arbitration table when vc arbitration uses the vc arbitration table. as a vc arbitration table is never used by this component this field will never be used. datasheet, volume 2 139 processor configuration registers 2.7.4 vc0rcap?vc0 resour ce capability register b/d/f/type: 0/1/0/mmr address offset: 110?113h reset value: 00000001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for port arbitration table offset (pato) 23 ro 0h reserved (rsvd) 22:16 ro 00h uncore reserved for maximum time slots (mts) 15 ro 0b uncore reject snoop transactions (rsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request 14:8 ro 0h reserved (rsvd) 7:0 ro 01h uncore port arbitration capability (pac) this field indicates types of port arbitration supported by the vc resource. this field is valid for a ll switch ports, root ports that support peer-to-peer traffic, and rcrbs, but not for pci express endpoint devices or root ports that do not support peer-to-peer traffic. each bit location within this fiel d corresponds to a port arbitration capability defined below. when more than one bit in this field is set, it indicates that the vc resource can be configured to provide different arbitration services. software selects among these capa bilities by writing to the port arbitration select field (see below). defined bit positions are: bit 0 non-configurable hardware-fixed arbitration scheme, such as., round robin (rr) bit 1 weighted round robin (wrr) arbitration with 32 phases bit 2 wrr arbitration with 64 phases bit 3 wrr arbitration with 128 phases bit 4 time-based wrr with 128 phases bit 5 wrr arbitration with 256 phases bits 6-7 reserved processor only supported arbitration indicates "non-configurable hardware-fixed arbitration scheme". processor configuration registers 140 datasheet, volume 2 2.7.5 vc0rctl?vc0 reso urce control register this register controls the resources associated with pci express* virtual channel 0. b/d/f/type: 0/1/0/mmr address offset: 114?117h reset value: 800000ffh access: ro, rw size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31 ro 1b uncore vc0 enable (vc0e) for vc0, this is hardwired to 1 and read only as vc0 can never be disabled. 30:27 ro 0h reserved (rsvd) 26:24 ro 000b uncore vc0 id (vc0id) assigns a vc id to the vc resource. for vc0, this is hardwired to 0 and read only. 23:20 ro 0h reserved (rsvd) 19:17 rw 000b uncore port arbitration select (pas) this field configures the vc resour ce to provide a particular port arbitration service. this field is valid for rcrbs, root ports that support peer to peer traffic, and switch ports, but not for pci express endpoint devices or root ports that do not support peer to peer traffic. the permissible value of this fi eld is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. this field does not affect the root port behavior. 16 ro 0h reserved (rsvd) 15:8 rw 00h uncore tc high vc0 map (tchvc0m) allow usage of high order tcs. bios should keep this field zeroed to allow usage of the reserved tc[3] for other purposes. 7:1 rw 7fh uncore tc/vc0 map (tcvc0m) this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0ro 1buncore tc0/vc0 map (tc0vc0m) traffic class 0 is always routed to vc0. datasheet, volume 2 141 processor configuration registers 2.7.6 vc0rsts?vc0 resource status register this register reports the virtual channel specific status. 2.7.7 peg_tc?pci express* co mpletion timeout register this register reports pci express* config uration control of pci express completion timeout related parameters that are not re quired by the pci express specification. b/d/f/type: 0/1/0/mmr address offset: 11a?11bh reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore vc0 negotiation pending (vc0np) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/1/0/mmr address offset: 208h access: rw bit access reset value rst/ pwr description 31:15 ro 000000000 00000000b reserved (rsvd) 14:12 rw 111b pci express completion timeout (peg_tc) this field determines the number of milliseconds the transaction layer will wait to receive an expected completion. to avoid hang conditions, the transaction layer will generate a dummy completion to the requestor if it does not receive the completion within this time period. 000 = disable 001 = reserved 010 = reserved 100 = reserved 101 = reserved 110 = reserved x11 = 48 ms ? for normal operation 11:0 ro 000000000 000b reserved (rsvd) processor configuration registers 142 datasheet, volume 2 2.7.8 eqctl0_1?lane 0/1 equa lization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane) b/d/f/type: 0/1/0/mmr address offset: da0?da3h reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0 , section 4.2.3 for de tails. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0 , section 4.2.3 for de tails. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. datasheet, volume 2 143 processor configuration registers 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. b/d/f/type: 0/1/0/mmr address offset: da0?da3h reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 144 datasheet, volume 2 2.7.9 eqctl2_3?lane 2/3 equa lization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane) b/d/f/type: 0/1/0/mmr address offset: da4?da7h reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. datasheet, volume 2 145 processor configuration registers 2.7.10 eqctl4_5?lane 4/5 equa lization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: da8?dabh reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. processor configuration registers 146 datasheet, volume 2 2.7.11 eqctl6_7?lane 6/7 equa lization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: dac?dafh reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. datasheet, volume 2 147 processor configuration registers 2.7.12 eqctl8_9?lane 8/9 equa lization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: db0?db3h reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. processor configuration registers 148 datasheet, volume 2 2.7.13 eqctl10_11?lane 10/11 eq ualization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: db4?db7h reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. datasheet, volume 2 149 processor configuration registers 2.7.14 eqctl12_13?lane 12/13 eq ualization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: db8?dbbh reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. processor configuration registers 150 datasheet, volume 2 2.7.15 eqctl14_15?lane 14/15 eq ualization control register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: dbc?dbfh reset value: 07080708h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31 ro 0h reserved (rsvd) 30:28 rw 000b uncore lane 1 downstream component receiver preset hint (dcrph1) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 27:24 rw 0111b uncore lane 1 downstream component transmitter preset (dctp1) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 23 ro 0h reserved (rsvd) 22:20 rw 000b uncore lane 1 upstream component receiver preset hint (ucrph1) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 19:16 rw 1000b uncore lane 1 upstream component transmitter preset (uctp1) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 15 ro 0h reserved (rsvd) 14:12 rw 000b uncore lane 0 downstream component receiver preset hint (dcrph0) receiver preset hint for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 11:8 rw 0111b uncore lane 0 downstream component transmitter preset (dctp0) transmitter preset for downstream component. the upstream component must pass on this value in the eq ts2?s. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 7ro 0h reserved (rsvd) 6:4 rw 000b uncore lane 0 upstream component receiver preset hint (ucrph0) receiver preset hint for upstream component. the upstream component may use this hint for receiver equalization. see the pcie base specification 3.0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. 3:0 rw 1000b uncore lane 0 upstream component transmitter preset (uctp0) transmitter preset for an upstream component. see the pcie base specification 3. 0, section 4.2.3 for details. the encodings are defined in section 4.2.3.2. datasheet, volume 2 151 processor configuration registers 2.7.16 eqcfg?equalization configuration register lane equalization control register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). b/d/f/type: 0/1/0/mmr address offset: dd8?ddbh reset value: f9404400h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:26 rw 3eh uncore full swing value (fs) fs is used to calculate the transmitter coefficients during equalization. default is 62d. note: all equalization presets? coefficients have been calculated using the default fs value of 62d. if fs is changed, the preset tables located in eqpreset* registers may need to be re- programmed to fulfill fs. fs = |cm1| + c0 + |cp1| (c0 > 0) 25:20 rw 14h uncore low frequency value (lf) lf is used to calculate the tr ansmitter coefficients during equalization. default is 20d. note: all equalization presets? coefficients have been calculated using the default lf value of 20d. if lf is changed, the preset tables located in eqpreset* registers may need to be re- programmed to fulfill lf. cm1 + c0 + cp1 > lf 19:16 ro 0h reserved (rsvd) 15 rw 0b uncore bypass phase 2 equalization (eqph2byp) if set, after phase 1 is complete, the ltssm will bypass phase 2 and 3 of equalization. 14 rw 1b uncore bypass phase 3 equalization (eqph3byp) if set, after phase 2 is complete, the ltssm will bypass phase 3 of equalization and go back to recovery.rcvrlock. 13 rw 0b uncore disable margining (margindis) when set, it will disable tx ma rgining during polling.compliance and recovery. 12:8 ro 0h reserved (rsvd) 7rw 0buncore gen3 bypass levels (g3byplvl) if this bit is set, the tx eq le vels will be bypassed only during gen3. the values of the bypass levels are found in the port eqbyplvlbnd* registers. when this bit is set, phase 2 and phase 3 equalization is expected to be bypassed. 6rw 0buncore global bypass levels (glbbyplvl) if this bit is set, the tx eq leve ls will be bypassed for all speeds. the values of the bypass levels are found in the port eqbyplvlbnd* registers. when this bit is set, phase 2 and phase 3 equalization is expected to be bypassed. processor configuration registers 152 datasheet, volume 2 5:2 rw 0h uncore bypass coefficients during phase 3 (bypcoefph3) bit [0]: controls the value of bit 7 in symbol 6 of eq ts1s during "bypass phase 3 adaptation" 1 = use preset 0 = use coefficients the preset is defined by the per-lane dctp field in eqctl register. coefficient values are defined within the appropriate eqpreset* register, using dctp as an index. bits [3:1]: undefined 1rw 0buncore bypass phase 3 adaptation fsm (bypadfsm) when set, when phase 3 is entere d, ?bypass? coe fficients will be sent to the link partner. when the coefficients are accepted by the link partner, no adaptation w ill be done, and phase 3 will be complete. this bit needs to be set before phase 3 start. 0ro 0h reserved (rsvd) b/d/f/type: 0/1/0/mmr address offset: dd8?ddbh reset value: f9404400h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description datasheet, volume 2 153 processor configuration registers 2.8 pci device 2 configuration space registers table 2-11. pci device 2 configur ation space register address map address offset register symbol register name reset value access 0?1h vid2 vendor identification 8086h ro 2?3h did2 device identification 0152h ro-v, ro-fw 4?5h pcicmd2 pci command 0000h rw, ro 6?7h pcists2 pci status 0090h ro, ro-v 8h rid2 revision identification 00h ro-fw 9?bh cc class code 030000h ro-v, ro ch cls cache line size 00h ro dh mlt2 master latency timer 00h ro eh hdr2 header type 00h ro fh rsvd reserved 0h ro 10?17h gttmmadr graphics translation table, memory mapped range address 000000000 0000004h ro, rw 18?1fh gmadr graphics memory range address 00000000 0000000ch rw, ro, rw-l 20?23h iobar i/o base address 00000001h rw, ro 24?2bh rsvd reserved 0h ro 2c?2dh svid2 subsystem vendor identification 0000h rw-o 2e?2fh sid2 subsystem identification 0000h rw-o 30?33h romadr video bios rom base address 00000000h ro 34h cappoint capabilities pointer 90h ro-v 35?3bh rsvd reserved 0h ro 3ch intrline interrupt line 00h rw 3dh intrpin interrupt pin 01h ro 3eh mingnt minimum grant 00h ro 3fh maxlat maximum latency 00h ro 40?61h rsvd reserved ? ? 62h msac multi size aperture control 02h rw, rw-k 63?ffh rsvd reserved ? ? processor configuration registers 154 datasheet, volume 2 2.8.1 vid2?vendor iden tification register this register combined with the device identification register uniquely identifies any pci device. 2.8.2 did2?device identification register this register combined with the vendor iden tification register uniquely identifies any pci device. this is a 16 bit value assigned to the processor graphics device. b/d/f/type: 0/2/0/pci address offset: 0?1h reset value: 8086h access: ro size: 16 bits bit access reset value rst/ pwr description 15:0 ro 8086h uncore vendor identification number (vid) pci standard identification for intel. b/d/f/type: 0/2/0/pci address offset: 2?3h reset value: 0152h access: ro-v, ro-fw size: 16 bits bit access reset value rst/ pwr description 15:4 ro-fw 015h uncore device identification number msb (did_msb) this is the upper part of a 16 bit value assigned to the graphics device. valid values: 15h 16h 3:2 ro-v 00b uncore device identification number ? sku (did_sku) those are bits 3:2 of the 16-bit value assigned to the processor graphics device. sku bits 3:2 server 10 1:0 ro-v 10b uncore device identification number lsb (did_lsb) this is the lower part of a 16 bi t value assigned to the processor graphics device. datasheet, volume 2 155 processor configuration registers 2.8.3 pcicmd2?pci command register this 16-bit register provides basic control over the igd's ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. b/d/f/type: 0/2/0/pci address offset: 4?5h reset value: 0000h access: rw, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:11 ro 0h reserved (rsvd) 10 rw 0b flr, uncore interrupt disable (intdis) this bit disables the device from asserting intx#. 0 = enable the assertion of this device's intx# signal. 1 = disable the assertion of this device's intx# signal. do_intx messages will not be sent to dmi. 9ro 0buncore fast back-to-back (fb2b) not implemented. hardwired to 0. 8ro 0buncore serr enable (serre) not implemented. hardwired to 0. 7ro 0buncore address/data stepping enable (adstep) not implemented. hardwired to 0. 6ro 0buncore parity error enable (perre) not implemented. hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd ignores any parity error that it detects and continues with normal operation. 5ro 0buncore video palette snooping (vps) this bit is hardwired to 0 to disable snooping. 4ro 0buncore memory write and invalidate enable (mwie) hardwired to 0. the igd does not support memory write and invalidate commands. 3ro 0buncore special cycle enable (sce) this bit is hardwired to 0. the igd ignores special cycles. 2rw 0b flr, uncore bus master enable (bme) 0 = disable igd bus mastering. 1 = enable the igd to function as a pci compliant master. 1rw 0b flr, uncore memory access enable (mae) this bit controls the igd's response to memory space accesses. 0 = disable. 1 = enable. 0rw 0b flr, uncore i/o access enable (ioae) this bit controls the igd's response to i/o space accesses. 0 = disable. 1 = enable. processor configuration registers 156 datasheet, volume 2 2.8.4 pcists2?pci status register pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcists also indicates the devsel# ti ming that has been set by the igd. b/d/f/type: 0/2/0/pci address offset: 6?7h reset value: 0090h access: ro, ro-v size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 ro 0b uncore detected parity error (dpe) since the igd does not detect parity, this bit is always hardwired to 0. 14 ro 0b uncore signaled system error (sse) the igd never asserts serr#; theref ore, this bit is hardwired to 0. 13 ro 0b uncore received master abort status (rmas) the igd never gets a master abort; therefore, this bit is hardwired to 0. 12 ro 0b uncore received target abort status (rtas) the igd never gets a target abort; therefore, this bit is hardwired to 0. 11 ro 0b uncore signaled target abort status (stas) hardwired to 0. the igd does not use target abort semantics. 10:9 ro 00b uncore devsel timing (devt) n/a. these bits are hardwired to "00". 8ro 0buncore master data parity error detected (dpd) since parity error response is hardwired to disabled (and the igd does not do any parity detection), this bit is hardwired to 0. 7ro 1buncore fast back-to-back (fb2b) hardwired to 1. the igd accepts fast back-to-back when the transactions are not to the same agent. 6ro 0buncore user defined format (udf) hardwired to 0. 5ro 0buncore 66 mhz pci capable (c66) n/a ? hardwired to 0. 4ro 1buncore capability list (clist) this bit is set to 1 to indicate th at the register at 34h provides an offset into the function's pci configuration space containing a pointer to the location of the first item in the list. 3ro-v 0b uncore interrupt status (intsts) this bit reflects the state of the interrupt in the device. only when the interrupt disable bit in the command register is a 0 and this interrupt status bit is a 1, will the devices intx# signal be asserted. 2:0 ro 0h reserved (rsvd) datasheet, volume 2 157 processor configuration registers 2.8.5 rid2?revision identification register this register contains the revision number for device 2 functions 0. these bits are read only and writes to this register have no effect. 2.8.6 cc?class code register this register contains the device programming interface information related to the sub- class code and base class code definition for the igd. this register also contains the base class code and the function sub-class in relation to the base class code. b/d/f/type: 0/2/0/pci address offset: 8h reset value: 00h access: ro-fw size: 8 bits bit access reset value rst/ pwr description 7:0 ro-fw 0h uncore revision identification number (rid) refer to the intel ? xeon ? processor e3-1200 v2 product family specification update for the value of the rid register. b/d/f/type: 0/2/0/pci address offset: 9?bh reset value: 030000h access: ro-v, ro size: 24 bits bit access reset value rst/ pwr description 23:16 ro-v 03h uncore base class code (bcc) this is an 8-bit value that indicates the base class code. 03h = display controller. 15:8 ro-v 00h uncore sub-class code (subcc) 00h = vga compatible. 7:0 ro 00h uncore programming interface (pi) 00h = display controller. processor configuration registers 158 datasheet, volume 2 2.8.7 cls?cache line size register the igd does not support this register as a pci slave. 2.8.8 mlt2?master la tency timer register the igd does not support the programmability of the master latency timer because it does not perform bursts. 2.8.9 hdr2?header type register this register contains the header type of the igd. b/d/f/type: 0/2/0/pci address offset: ch reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore cache line size (cls) this field is hardwired to 0s. th e igd as a pci compliant master does not use the memory write and invalidate command and, in general, does not perform operations based on cache line size. b/d/f/type: 0/2/0/pci address offset: dh reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore master latency timer count value (mltcv) hardwired to 0s. b/d/f/type: 0/2/0/pci address offset: eh reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7ro 0buncore multi function status (mfunc) this bit indicates if the device is a multi-function device. the value of this register is hardwired to 0; processor graphics is a single function. 6:0 ro 00h uncore header code (h) this is a 7-bit value that indica tes the header code for the igd. this code has the value 00h, indicating a type 0 configuration space format. datasheet, volume 2 159 processor configuration registers 2.8.10 gttmmadr?graphics translation table, memory mapped range address register this register requests allocation for the combined graphics translation table modification range and memory mapped range. the range requires 4 mb combined for mmio and global gtt aperture, with 2 mb of that used by mmio and 2 mb used by gtt. gttadr will begin at (gttmmadr + 2 mb) wh ile the mmio base address will be the same as gttmmadr. for the global gtt, this range is defined as a memory bar in graphics device configuration space. it is an alias into which software is required to write page table entry values (ptes). software may read pte values from the global graphics translation table (gtt). ptes cannot be wri tten directly into the global gtt memory area. the device snoops writes to this region in order to invalidate any cached translations within the various tlbs implemented on-chip. the allocation is for 4 mb and the base address is defined by bits 38:22. b/d/f/type: 0/2/0/pci address offset: 10?17h reset value: 0000000000000004h access: ro, rw size: 64 bits bit access reset value rst/ pwr description 63:39 rw 0000000h flr, uncore reserved for memory base address (rsvdrw) must be set to 0 since addressi ng above 512 gb is not supported. 38:22 rw 00000h flr, uncore memory base address (mba) set by the operating system, these bits correspond to address signals 38:22. 4 mb combined for mmio and global gtt table aperture (2 mb for mmio and 2 mb for gtt). 21:4 ro 00000h uncore address mask (adm) hardwired to 0s to indicate at least 4 mb address range. 3ro 0buncore prefetchable memory (prefmem) hardwired to 0 to prevent prefetching. 2:1 ro 10b uncore memory type (memtyp) 00 = to indicate 32 bit base address 01 = reserved 10 = to indicate 64 bit base address 11 = reserved 0ro 0buncore memory/io space (mios) hardwired to 0 to indicate memory space. processor configuration registers 160 datasheet, volume 2 2.8.11 gmadr?graphics memo ry range address register gmadr is the pci aperture used by s/w to access tiled graphics surfaces in a linear fashion. b/d/f/type: 0/2/0/pci address offset: 18?1fh reset value: 000000000000000ch access: rw, ro, rw-l size: 64 bits bit access reset value rst/ pwr description 63:39 rw 0000000h flr, uncore reserved for memory base address (rsvdrw) must be set to 0 since addressing above 512 gb is not supported. 38:29 rw 00000000 00b flr, uncore memory base address (mba) set by the os, these bits correspond to address signals 38:29. 28 rw-l 0b flr, uncore 512 mb address mask (admsk512) this bit is either part of the memory base address (rw) or part of the address mask (ro), depending on the value of msac[2:1]. see section 2.8.21, ?msac?multi size aperture control register? on page 164 for details. 27 rw-l 0b flr, uncore 256 mb address mask (admsk256) this bit is either part of the memory base address (rw) or part of the address mask (ro), depending on the value of msac[2:1]. see section 2.8.21, ?msac?multi size aperture control register? on page 164 for details. 26:4 ro 000000h uncore address mask (adm) hardwired to 0s to indicate at least 128 mb address range. 3ro 1buncore prefetchable memory (prefmem) hardwired to 1 to enable prefetching. 2:1 ro 10b uncore memory type (memtyp) 00 = 32-bit address. 10 = 64-bit address 0ro 0buncore memory/io space (mios) hardwired to 0 to indicate memory space. datasheet, volume 2 161 processor configuration registers 2.8.12 iobar?i/o base address register this register provides the base offset of th e i/o registers within device 2. bits 15:6 are programmable allowing the i/o base to be located anywhere in 16bit i/o address space. bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of i/o space are decoded. access to the 8bs of i/o space is allowed in pm state d0 when i/o enable (pcicmd bit 0) set. acce ss is disallowed in pm states d1?d3 or if i/o enable is clear or if device 2 is turned o ff or if internal graphics is disabled thru the fuse or fuse override mechanisms. access to this i/o bar is independent of vga functionality within device 2. if accesses to this i/o bar are allowed, then all 8, 16 or 32-bit i/o cycles from ia cores that falls within the 8b are claimed. 2.8.13 svid2?subsystem vendor identification register this register is used to uniquely identify the subsystem where the pci device resides. b/d/f/type: 0/2/0/pci address offset: 20?23h reset value: 00000001h access: rw, ro size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:6 rw 000h flr, uncore io base address (iobase) set by the os, these bits correspond to address signals 15:6. 5:3 ro 0h reserved (rsvd) 2:1 ro 00b uncore memory type (memtype) hardwired to 0s to in dicate 32-bit address. 0ro 1buncore memory/io space (mios) hardwired to "1" to indicate i/o space. b/d/f/type: 0/2/0/pci address offset: 2c?2dh reset value: 0000h access: rw-o size: 16 bits bit access reset value rst/ pwr description 15:0 rw-o 0000h uncore subsystem vendor id (subvid) this value is used to identify th e vendor of the subsystem. this register should be programmed by bios during boot-up. once written, this register becomes read-only. this register can only be cleared by a reset. processor configuration registers 162 datasheet, volume 2 2.8.14 sid2?subsystem identification register this register is used to uniquely identify the subsystem where the pci device resides. 2.8.15 romadr?video bios rom base address register the igd does not use a separate bios rom; th erefore this register is hardwired to 0s. 2.8.16 cappoint?capabil ities pointer register this register points to a linked list of capabilities implemented by this device. b/d/f/type: 0/2/0/pci address offset: 2e?2fh reset value: 0000h access: rw-o size: 16 bits bit access reset value rst/ pwr description 15:0 rw-o 0000h uncore subsystem identification (subid) this value is used to identify a particular subsystem. this field should be programmed by bios during boot-up. once written, this register becomes read-only. this register can only be cleared by a reset. b/d/f/type: 0/2/0/pci address offset: 30?33h reset value: 00000000h access: ro size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31:18 ro 0000h uncore rom base address (rba) hardwired to 0s. 17:11 ro 00h uncore address mask (admsk) hardwired to 0s to indicate 256 kb address range. 10:1 ro 0h reserved (rsvd) 0ro 0buncore rom bios enable (rbe) 0 = rom not accessible. b/d/f/type: 0/2/0/pci address offset: 34h reset value: 90h access: ro-v size: 8 bits bit access reset value rst/ pwr description 7:0 ro-v 90h uncore capabilities pointer value (cpv) this field contains an offset into the function's pci configuration space for the first item in the new capabilities linked list, the msi capabilities id registers at address 90h or the power management capability at d0h. this value is determined by the configuration in capl[0]. datasheet, volume 2 163 processor configuration registers 2.8.17 intrline?interrupt line register this 8-bit register is used to communicate interrupt line routing information. it is read/write and must be implemented by the device. post software will write the routing information into this register as it initializes and configures the system. the value in this register tells which inpu t of the system interrupt controller(s) the device's interrupt pin is connected to. the device itself does not use this value; rather it is used by device drivers and operating systems to determine priority and vector information. 2.8.18 intrpin?interrupt pin register this register tells which interrupt pin the device uses. the integrated graphics device uses inta#. 2.8.19 mingnt?minimum grant register the integrated graphics device has no requirement for the settings of latency timers. b/d/f/type: 0/2/0/pci address offset: 3ch reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore interrupt connection (intcon) this field is used to comm unicate interrupt line routing information. post software writ es the routing information into this register as it initializes an d configures the system. the value in this register indicates to which input of the system interrupt controller the device's in terrupt pin is connected. b/d/f/type: 0/2/0/pci address offset: 3dh reset value: 01h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 01h uncore interrupt pin (intpin) as a single function device, the igd specifies inta# as its interrupt pin. 01h = inta#. b/d/f/type: 0/2/0/pci address offset: 3eh reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore minimum grant value (mgv) the igd does not burst as a pci compliant master. processor configuration registers 164 datasheet, volume 2 2.8.20 maxlat?maximum latency register the integrated graphics device has no requ irement for the settings of latency timers. 2.8.21 msac?multi size aperture control register this register determines the size of the gr aphics memory aperture in function 0 and in the trusted space. only the system bios w ill write this register based on pre- boot address allocation efforts, but the graphics may read this register to determine the correct aperture size. system bios needs to save this value on boot so that it can reset it correctly during s3 resume. b/d/f/type: 0/2/0/pci address offset: 3fh reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore maximum latency value (mlv) the igd has no specific requirements for how often it needs to access the pci bus. b/d/f/type: 0/2/0/pci address offset: 62h reset value: 02h access: rw, rw-k size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:4 rw 0h uncore reserved rw (rsvdrw) scratch bits only -- have no physical effect on hardware 3ro 0h reserved (rsvd) 2rw-k 0b uncore untrusted aperture size high (lhsash) this field is used in conjunction with lhsasl. the description below is for both fiel ds (lhsash & lhsasl). 11 = bits [28:27] of gmadr are ro, allowing 512 mb of gmadr 10 = illegal programming 01 = bit [28] of gmadr is rw but bit [27] of gmadr is ro, allowing 256 mb of gmadr 00 = bits [28:27] of gmadr are rw, allowing 128 mb of gmadr 1rw-k 1b uncore untrusted aperture size low (lhsasl) this field is used in conjunct ion with lhsash. the description below is for both fields (lhsash & lhsasl). 11 = bits [28:27] of gmadr are ro, allowing 512 mb of gmadr 10 = illegal programming 01 = bit [28] of gmadr is rw but bit [27] of gmadr is ro, allowing 256 mb of gmadr 00 = bits [28:27] of gmadr are rw, allowing 128 mb of gmadr 0ro 0h reserved (rsvd) datasheet, volume 2 165 processor configuration registers 2.9 device 2 io registers 2.9.1 index?mmio address register mmio_index: a 32 bit i/o write to this port loads the offset of the mmio register or offset into the gtt that needs to be accessed. an i/o read returns the current value of this register. this mechanism to access internal graphics mmio registers must not be used to access vga i/o registers which are mapped through the mmio space. vga registers must be accessed directly through the dedicated vga i/o ports. 2.9.2 data?mmio data register mmio_data: a 32-bit i/o write to this port is re-directed to the mmio register/gtt location pointed to by the mmio-index register . a 32-bit i/o read to this port is re- directed to the mmio register/gtt location pointed to by the mmio-index register. table 2-12. device 2 io register address map address offset register symbol register name reset value access 0?3h index mmio address register 00000000h rw 4?7h data mmio data register 00000000h rw b/d/f/type: 0/2/0/pci io address offset: 0?3h reset value: 00000000h access: rw size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:21 ro 0h reserved (rsvd) 20:2 rw 00000h flr, uncore register/gtt offset (reggtto) this field selects any one of the dword registers within the mmio register space of device 2 if the target is mmio registers. this field selects a gtt offset if the target is the gtt. 1:0 rw 00b flr, uncore target (targ) 00 = mmio registers 01 = gtt 1x = reserved b/d/f/type: 0/2/0/pci io address offset: 4?7h reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h flr, uncore mmio data window (data) this field is the data field associated with the io2mmio access. processor configuration registers 166 datasheet, volume 2 2.10 pci device 6 registers table 2-13. pci device 6 regist er address map (sheet 1 of 2) address offset register symbol register name reset value access 0?1h vid vendor identification 8086h ro 2?3h did device identification 015dh ro-fw 4?5h pcicmd pci command 0000h rw, ro 6?7h pcists pci status 0010h rw1c, ro, ro- v 8h rid revision identification 00h ro-fw 9?bh cc class code 060400h ro ch cl cache line size 00h rw dh rsvd reserved 0h ro eh hdr header type 81h ro fh rsvd reserved 0h ro 18h pbusn primary bus number 00h ro 19h sbusn secondary bus number 00h rw 1ah subusn subordinate bus number 00h rw 1bh rsvd reserved 0h ro 1ch iobase i/o base address f0h rw 1dh iolimit i/o limit address 00h rw 1e?1fh ssts secondary status 0000h rw1c, ro 20?21h mbase memory base address fff0h rw 22?23h mlimit memory limit address 0000h rw 24?25h pmbase prefetchable memory base address fff1h rw, ro 26?27h pmlimit prefetchable memory limit address 0001h rw, ro 28?2bh pmbaseu prefetchable memory base address upper 00000000h rw 2c?2fh pmlimitu prefetchable memory limit address upper 00000000h rw 30?33h rsvd reserved 0h ro 34h capptr capabilities pointer 88h ro 35?3bh rsvd reserved 0h ro 3ch intrline interrupt line 00h rw 3dh intrpin interrupt pin 01h rw-o, ro 3e?3fh bctrl bridge control 0000h ro, rw 40?7fh rsvd reserved 0h ro 80?83h pm_capid power management capabilities c8039001h ro, ro-v 84?87h pm_cs power management control/status 00000008h ro, rw 88?8bh ss_capid subsystem id and vendor id capabilities 0000800dh ro 8c?8fh ss subsystem id and subsystem vendor id 00008086h rw-o datasheet, volume 2 167 processor configuration registers 2.10.1 vid?vendor identification register this register combined with the device identification regi ster uniquely identify any pci device. 90?91h msi_capid message signaled interrupts capability id a005h ro 92?93h mc message control 0000h ro, rw 94?97h ma message address 00000000h rw, ro 98?99h md message data 0000h rw 9a?9fh rsvd reserved 0h ro a0?a1h peg_capl pci express-g capability list 0010h ro a2?a3h peg_cap pci express-g capabilities 0142h ro, rw-o a4?a7h dcap device capabilities 00008000h ro, rw-o a8?a9h dctl device control 0000h ro, rw aa?abh dsts device status 0000h ro, rw1c ac?afh lcap link capabilities 0521cc42h ro, rw-o, ro- v, r w - o v b0?b1h lctl link control 0000h ro, rw, rw-v b2?b3h lsts link status 1001h rw1c, ro-v, ro b4?b7h slotcap slot capabilities 00040000h rw-o, ro b8?b9h slotctl slot control 0000h ro ba?bbh slotsts slot status 0000h ro, ro-v, rw1c bc?bdh rctl root control 0000h rw, ro be?cbh rsvd reserved ? ? cc?cfh lcap2 link capabilities 2 00000006h ro-v d0?d1h rsvd reserved 0002h rws, rws-v table 2-13. pci device 6 regist er address map (sheet 2 of 2) address offset register symbol register name reset value access b/d/f/type: 0/6/0/pci address offset: 0?1h reset value: 8086h access: ro size: 16 bits bit access reset value rst/ pwr description 15:0 ro 8086h uncore vendor identification (vid ) pci standard identification for intel. processor configuration registers 168 datasheet, volume 2 2.10.2 did?device iden tification register this register combined with the vendor iden tification register uniquely identifies any pci device. 2.10.3 pcicmd?pci command register b/d/f/type: 0/6/0/pci address offset: 2?3h reset value: 015dh access: ro-fw size: 16 bits bit access reset value rst/ pwr description 15:0 ro-fw 015dh uncore device identification number msb (did_msb ) identifier assigned to the processo r root port (virtual pci-to-pci bridge, pci express graphics port). b/d/f/type: 0/6/0/pci address offset: 4?5h reset value: 0000h access: rw, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:11 ro 0h reserved (rsvd) 10 rw 0b uncore inta assertion disable (intaad ) 0 = this device is permitted to generate inta interrupt messages. 1 = this device is prevented from generating interrupt messages. any inta emulation interrupts already asserted must be de-asserted when this bit is set. only affects interrupts generated by the device (pci inta from a pme or hot-plug event) controlled by this command register. it does not affect upstream msis, upstream pci inta-intd assert and deassert messages. note: pci express* hot-plug is not supported on the processor. 9ro 0buncore fast back-to-back enable (fb2b ) not applicable or implem ented. hardwired to 0. datasheet, volume 2 169 processor configuration registers 8rw 0buncore serr# message enable (serre ) this bit controls the root port?s serr# messaging. the processor communicates the serr# condition by sending an serr message to the pch. this bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the root complex. note that errors are reported if enabled either through this bit or through the pci expre ss* specific bits in the device control register. in addition, for type 1 configuration space header devices, this bit, when set, enables transmissi on by the primary interface of err_nonfatal and err_fatal error messages forwarded from the secondary interface. this bit does not affect the transmission of forwarded err_cor messages. 0 = the serr message is generated by the root port only under conditions enabled individually through the device control register. 1 = the root port is enabled to generate serr messages which will be sent to the pch for specific root port error conditions generated/detected or received on the secondary side of the virtual pci to pci bridge. the status of serrs generated is reported in the pcists register. 7ro 0h reserved (rsvd) 6rw 0buncore parity error response enable (perre ) this bit controls whether or not the master data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register can not be set. 1 = master data parity error bit in pci status register can be set. 5ro 0buncore vga palette snoop (vgaps ) not applicable or impleme nted. hardwired to 0. 4ro 0buncore memory write and invalidate enable (mwie ) not applicable or impleme nted. hardwired to 0. 3ro 0buncore special cycle enable (sce ) not applicable or impleme nted. hardwired to 0. b/d/f/type: 0/6/0/pci address offset: 4?5h reset value: 0000h access: rw, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 170 datasheet, volume 2 2rw 0buncore bus master enable (bme ) this bit controls the ability of the peg port to forward memory read/write requests in the upstream direction. 0 = this device is prevented from making memory requests to its primary bus. according to pci specification, as msi interrupt messages are in-ban d memory writes, disabling the bus master enable bit prevents this device from generating msi interrupt messages or passing them from its secondary bus to its primary bus. upstream memory writes/reads, peer writes/reads , and msis will all be treated as illegal cycles. writes are ab orted. reads are aborted and will return unsupported request status (or master abort) in its completion packet 1 = this device is allowed to issue requests to its primary bus. completions for previously issued memory read requests on the primary bus will be issued when the data is available. this bit does not affect forwarding of completions from the primary interface to the secondary interface. 1rw 0buncore memory access enable (mae ) 0 = all of device's memory space is disabled. 1 = enable the memory and pre-fetchable memory address ranges defined in the mbase, mlimit, pmbase, and pmlimit registers. 0rw 0buncore io access enable (ioae ) 0 = all of device?s i/o space is disabled. 1 = enable the i/o address range defined in the iobase, and iolimit registers. b/d/f/type: 0/6/0/pci address offset: 4?5h reset value: 0000h access: rw, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description datasheet, volume 2 171 processor configuration registers 2.10.4 pcists?pci status register this register reports the occurrence of error conditions associated with primary side of the "virtual" host-pci express brid ge embedded within the root port. b/d/f/type: 0/6/0/pci address offset: 6?7h reset value: 0010h access: rw1c, ro, ro-v size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 rw1c 0b uncore detected parity error (dpe ) this bit is set by a function whenever it receives a poisoned tlp, regardless of the state the parity error response bit in the command register. on a function with a type 1 configuration header, the bit is set when the poisoned tlp is received by its primary side. reset value of this bit is 0b. this bit will be set only for completions of requests encountering ecc error in dram. poisoned peer-2-peer posted forwar ded will not set this bit. they are reported at the receiving port. 14 rw1c 0b uncore signaled system error (sse ) this bit is set when this device sends an serr due to detecting an err_fatal or err_nonfatal condition and the serr enable bit in the command register is '1 '. both received (if enabled by bctrl1[1]) and internally detected error messages do not affect this field. 13 ro 0b uncore received master abort status (rmas): this bit is set when a requester receives a completion with unsupported request completion status. on a function with a type 1 configuration header, the bit is set when the unsupported request is received by its primary side. not applicable. there is no ur on primary interface 12 ro 0b uncore received target abort status (rtas ) this bit is set when a requester receives a completion with completer abort completion status. on a function with a type 1 configuration header, the bit is set when the comp leter abort is received by its primary side. reset value of this bit is 0b. not applicable or implemented. ha rdwired to 0. the concept of a completer abort does not exist on primary side of this device. 11 ro 0b uncore signaled target abort status (stas): this bit is set when a function co mpletes a posted or non-posted request as a completer abort error. this applies to a function with a type 1 configuration header when the completer abort was generated by its primary side. reset value of this bit is 0b. not applicable or implemented. ha rdwired to 0. the concept of a target abort does not exist on primary side of this device. 10:9 ro 00b uncore devselb timing (devt ) this device is not the subtractively decoded device on bus 0. this bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. does not apply to pci express and must be hardwired to 00b. processor configuration registers 172 datasheet, volume 2 2.10.5 rid?revision iden tification register this register contains the revision number of the processor root port. these bits are read only and writes to this register have no effect. 8rw1c 0b uncore master data parity error (pmdpe ) this bit is set by a requester (primary side for type 1 configuration space header function) if the parity error response bit in the command register is 1b and either of the following two conditions occurs: ? requester receives a co mpletion marked poisoned ? requester poisons a write request if the parity error response bit is 0b, this bit is never set. reset value of this bit is 0b. this bit will be set only for comple tions of requests encountering ecc error in dram. poisoned peer-2-peer posted forwarded will not set this bit. they are reported at the receiving port. 7ro 0buncore fast back-to-back (fb2b ) not applicable or implem ented. hardwired to 0. 6ro 0h reserved (rsvd) 5ro 0buncore 66/60mhz capability (cap66 ) not applicable or implem ented. hardwired to 0. 4ro 1buncore capabilities list (capl ) indicates that a capabilities list is present. hardwired to 1. 3ro-v 0b uncore intx status (intas ) this bit indicates that an interru pt message is pe nding internally to the device. only pme and hot-plug sources feed into this status bit (not pci inta?intd assert and deassert messages). the inta assertion disable bit, pcicmd1[10], has no effect on this bit. inta emulation interrupts rece ived across the link are not reflected in this bit. note: pci express* hot-plug is not supported on the processor. 2:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/pci address offset: 6?7h reset value: 0010h access: rw1c, ro, ro-v size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description b/d/f/type: 0/6/0/pci address offset: 8h reset value: 00h access: ro-fw size: 8 bits bit access reset value rst/ pwr description 7:0 ro-fw 0h uncore revision identification number (rid ) this is an 8-bit value that indi cates the revision identification number for the root port. refer to the intel ? xeon ? processor e3-1200 v2 product family specification update for the value of the rid register. datasheet, volume 2 173 processor configuration registers 2.10.6 cc?class code register this register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. 2.10.7 cl?cache line size register 2.10.8 hdr?header type register b/d/f/type: 0/6/0/pci address offset: 9?bh reset value: 060400h access: ro size: 24 bits bit access reset value rst/ pwr description 23:16 ro 06h uncore base class code (bcc) indicates the base class code for this device. this code has the value 06h indicating a bridge device. 15:8 ro 04h uncore sub-class code (subcc) indicates the sub-class code for this device. the code is 04h indicating a pci to pci bridge. 7:0 ro 00h uncore programming interface (pi) indicates the programming interface of this device. this value does not specify a particular register set layout and provides no practical use for this device. b/d/f/type: 0/6/0/pci address offset: ch reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore cache line size (cls ) implemented by pci express devices as a read-write field for legacy compatibility purposes but has no impact on any pci express device functionality. b/d/f/type: 0/6/0/pci address offset: eh reset value: 81h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 81h uncore header type register (hdr) device 1 returns 81h to indicate that this is a multi function device with bridge header layout. device 6 returns 01h to indicate that this is a single function device with bridge header layout. processor configuration registers 174 datasheet, volume 2 2.10.9 pbusn?primary bus number register this register identifies that this "virtual" host-pci express* bridge is connected to pci bus 0. 2.10.10 sbusn?secondary bus number register this register identifies the bus number assigned to the second bus side of the "virtual" bridge; that is, to pci express-g. this num ber is programmed by the pci configuration software to allow mapping of configuration cycles to pci express-g. 2.10.11 subusn?subordinate bus number register this register identifies the subordinate bus (if any) that resides at the level below pci express-g. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci express-g. b/d/f/type: 0/6/0/pci address offset: 18h reset value: 00h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 00h uncore primary bus number (busn) configuration software typically programs this field with the number of the bus on the primary side of the bridge. since the processor root port is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. b/d/f/type: 0/6/0/pci address offset: 19h reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore secondary bus number (busn ) this field is programmed by configuration software with the bus number assigned to pci express-g. b/d/f/type: 0/6/0/pci address offset: 1ah reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore subordinate bus number (busn ) this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the processor root port bridge. when only a single pci device resides on the pci express-g segment, this register will contain the same value as the sbusn1 register. datasheet, volume 2 175 processor configuration registers 2.10.12 iobase?i/o base address register this register controls the processor to pci express-g i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for th e purpose of address decode address bits a[11:0] are treated as 0. thus the bottom of the defined i/o address range will be aligned to a 4 kb boundary. 2.10.13 iolimit?i/o limit address register this register controls the processor to pci express-g i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for th e purpose of address decode address bits a[11:0] are assumed to be fffh. thus, the to p of the defined i/o address range will be at the top of a 4 kb aligned address block. b/d/f/type: 0/6/0/pci address offset: 1ch reset value: f0h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:4 rw fh uncore i/o address base (iobase:) this field corresponds to a[15:12] of the i/o addresses passed by the root port to pci express-g . 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/pci address offset: 1dh reset value: 00h access: rw size: 8 bits bios optimal default 0h bit access reset value rst/ pwr description 7:4 rw 0h uncore i/o address limit (iolimit ) this field corresponds to a[15:12] of the i/o address limit of the root port. devices between this upper limit and iobase1 will be passed to the pci express hierarchy associated with this device. 3:0 ro 0h reserved (rsvd) processor configuration registers 176 datasheet, volume 2 2.10.14 ssts?secondary status register ssts is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, pc i express-g side) of the "virtual" pci-pci bridge embedded within the processor. b/d/f/type: 0/6/0/pci address offset: 1e?1fh reset value: 0000h access: rw1c, ro size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15 rw1c 0b uncore detected parity error (dpe ) this bit is set by the secondary side for a type 1 configuration space header device whenever it receives a poisoned tlp, regardless of the state of the parity error response enable bit in the bridge control register. 14 rw1c 0b uncore received system error (rse ) this bit is set when the secondary side for a type 1 configuration space header device receives an err_fatal or err_nonfatal. 13 rw1c 0b uncore received master abort (rma ) this bit is set when the secondar y side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a comple tion with unsupported request completion status. 12 rw1c 0b uncore received target abort (rta ) this bit is set when the secondar y side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a comp letion with completer abort completion status. 11 ro 0b uncore signaled target abort (sta ) not applicable or implemented. hardwired to 0. the processor does not generate target aborts (the root port will never complete a request using the completer abort completion status). ur detected inside the processo r (such as in imph/mc will be reported in primary side status) 10:9 ro 00b uncore devselb timing (devt ) not applicable or implem ented. hardwired to 0. 8rw1c 0b uncore master data parity error (smdpe ) when set indicates that the proc essor received across the link (upstream) a read data completion poisoned tlp (ep=1 ). this bit can only be set when the parity error enable bit in the bridge control register is set. 7ro 0buncore fast back-to-back (fb2b ) not applicable or implem ented. hardwired to 0. 6ro 0h reserved (rsvd) 5ro 0buncore 66/60 mhz capability (cap66 ) not applicable or implem ented. hardwired to 0. 4:0 ro 0h reserved (rsvd) datasheet, volume 2 177 processor configuration registers 2.10.15 mbase?memory ba se address register this register controls the processor to pci express-g non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/6/0/pci address offset: 20?21h reset value: fff0h access: rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:4 rw fffh uncore memory address base (mbase) this field corresponds to a[31: 20] of the lower limit of the memory range that will be passed to pci express-g. 3:0 ro 0h reserved (rsvd) processor configuration registers 178 datasheet, volume 2 2.10.16 mlimit?memory limit address register this register controls the processor to pci express-g non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read-only and return zeroes when read. th is register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: memory range covered by mbase and mlimit registers are used to map non- prefetchable pci express-g address ranges (typically where control/status memory- mapped i/o data structures of the grap hics controller will reside) and pmbase and pmlimit are used to map prefetchable address ranges (typically graphics local memory). this segregation allows applicatio n of uswc space attribute to be performed in a true plug-and-play manner to the pr efetchable address range for improved processor-pci express memory access performance. note: configuration software is responsible fo r programming all address range registers (prefetchable, non-prefetchable) with the va lues that provide exclusive address ranges; that is, prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the processor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured. b/d/f/type: 0/6/0/pci address offset: 22?23h reset value: 0000h access: rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:4 rw 000h uncore memory address limit (mlimit) this field corresponds to a[31:20] of the upper limit of the address range passed to pci express-g. 3:0 ro 0h reserved (rsvd) datasheet, volume 2 179 processor configuration registers 2.10.17 pmbase?prefetchable me mory base address register this register in conjunction with the corresponding upper base address register controls the processor to pci express-g pr efetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39 :32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/6/0/pci address offset: 24?25h reset value: fff1h access: rw, ro size: 16 bits bit access reset value rst/ pwr description 15:4 rw fffh uncore prefetchable memory base address (pmbase) this field corresponds to a[31: 20] of the lower limit of the memory range that will be passed to pci express-g. 3:0 ro 1h uncore 64-bit address support (as64) this field indicates that the upper 32 bits of the prefetchable memory region base address are contained in the prefetchable memory base upper address register at 28h. processor configuration registers 180 datasheet, volume 2 2.10.18 pmlimit?prefetchable me mory limit address register this register in conjunction with the corresponding upper limit address register controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bi ts of the upper limit address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fff ffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (that is, prefetchable) from the processor perspective. b/d/f/type: 0/6/0/pci address offset: 26?27h reset value: 0001h access: rw, ro size: 16 bits bit access reset value rst/ pwr description 15:4 rw 000h uncore prefetchable memory address limit (pmlimit) this field corresponds to a[31:20] of the upper limit of the address range passed to pci express-g. 3:0 ro 1h uncore 64-bit address support (as64b ) this field indicates that the up per 32 bits of the prefetchable memory region limit address are contained in the prefetchable memory base limit address register at 2ch datasheet, volume 2 181 processor configuration registers 2.10.19 pmbaseu?prefetchable memory base address upper register the functionality associated with this register is present in the peg design implementation. this register in conjunc tion with the corresponding upper base address register controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 39-bit address. the lower 7 bits of the upper base address register are read/write and correspond to address bits a[38 :32] of the 39-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. b/d/f/type: 0/6/0/pci address offset: 28?2bh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore prefetchable memory base address (pmbaseu ) this field corresponds to a[63: 32] of the lower limit of the prefetchable memory range that will be passed to pci express- g. processor configuration registers 182 datasheet, volume 2 2.10.20 pmlimitu?prefe tchable memory limit address upper register the functionality associated with this register is present in the peg design implementation. this register, in conjunction with the co rresponding upper limit address register, controls the processor to pci express-g prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 39-bit address. the lower 7 bi ts of the upper limit address register are read/write and correspond to address bits a[38:32] of the 39-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fff ffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (that is, prefetchable) from the processor perspective. b/d/f/type: 0/6/0/pci address offset: 2c?2fh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore prefetchable memory address limit (pmlimitu) this field corresponds to a[63: 32] of the upper limit of the prefetchable memory range that will be passed to pci express-g. datasheet, volume 2 183 processor configuration registers 2.10.21 capptr?capabilit ies pointer register the capabilities pointer provides the address o ffset to the location of the first entry in this device's linked list of capabilities. 2.10.22 intrline?interrupt line register this register contains interrupt line routing information. the device itself does not use this value; rather it is used by device drivers and operating systems to determine priority and vector information. b/d/f/type: 0/6/0/pci address offset: 34h reset value: 88h access: ro size: 8 bits bit access reset value rst/ pwr description 7:0 ro 88h uncore first capability (capptr1) the first capability in the list is the subsystem id and subsystem vendor id capability. b/d/f/type: 0/6/0/pci address offset: 3ch reset value: 00h access: rw size: 8 bits bit access reset value rst/ pwr description 7:0 rw 00h uncore interrupt connection (intcon) this field is used to comm unicate interrupt line routing information. bios requirement: post software writes the routing information into this register as it initializes and configures the system. the value indicates to which input of the system interrupt controller th is device's interrupt pin is connected. processor configuration registers 184 datasheet, volume 2 2.10.23 intrpin?inte rrupt pin register this register specifies which interrupt pin this device uses. 2.10.24 bctrl?bridge control register this register provides extensions to the pc icmd register that are specific to pci-pci bridges. the bctrl provides additional cont rol for the secondary interface (that is, pci express-g) as well as some bits that affect the overall behavior of the "virtual" host- pci express bridge embedded within the pr ocessor; such as vga compatible address ranges mapping. b/d/f/type: 0/6/0/pci address offset: 3dh reset value: 01h access: rw-o, ro size: 8 bits bit access reset value rst/ pwr description 7:3 ro 00h uncore reserved (rsvd) 2:0 rw-o 1h uncore interrupt pin (intpin ) as a multifunction device, the pc i express device may specify any intx (x=a,b,c,d) as its interrupt pin. the interrupt pin register tells wh ich interrupt pin the device (or device function) uses. a value of 1 corresponds to inta# (default) a value of 2 corresponds to intb# a value of 3 corresponds to intc# a value of 4 corresponds to intd# devices (or device functions) that do not use an interrupt pin must put a 0 in this register. the values 05h through ffh are reserved. this register is write once. bios must set this register to select the intx to be used by this root port. b/d/f/type: 0/6/0/pci address offset: 3e?3fh reset value: 0000h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 ro 0b uncore discard timer serr# enable (dtserre ) not applicable or implem ented. hardwired to 0. 10 ro 0b uncore discard timer status (dtsts ) not applicable or implem ented. hardwired to 0. 9ro 0buncore secondary discard timer (sdt) not applicable or implem ented. hardwired to 0. 8ro 0buncore primary discard timer (pdt) not applicable or implem ented. hardwired to 0. 7ro 0buncore fast back-to-back enable (fb2ben) not applicable or implem ented. hardwired to 0. datasheet, volume 2 185 processor configuration registers 6rw 0buncore secondary bus reset (sreset) setting this bit triggers a hot reset on the corresponding pci express port. this will force the ltssm to transition to the hot reset state (using recovery) from l0, l0s, or l1 states. 5ro 0buncore master abort mode (mamode) does not apply to pci express. hardwired to 0. 4rw 0buncore vga 16-bit decode (vga16d) enables the pci-to-pci bridge to provide 16-bit decoding of vga i/o address precluding the decoding of alias addresses every 1 kb. this bit only has meaning if bit 3 (vga enable) of this register is also set to 1, enabling vga i/o decoding and forwarding by the bridge. 0 = execute 10-bit address decodes on vga i/o accesses. 1 = execute 16-bit address decodes on vga i/o accesses. 3rw 0buncore vga enable (vgaen) controls the routing of processor initiated transactions targeting vga compatible i/o and memo ry address ranges. see the vgaen/mdap table in device 0, offset 97h[0]. 2rw 0buncore isa enable (isaen) needed to exclude legacy resource decode to route isa resources to legacy decode path. modifies the response by the root port to an i/o access issued by the processor that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and io limit registers. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to pci express-g. 1 = the root port will not forward to pci express-g any i/o transactions addressing the last 768 bytes in each 1 kb block even if the addresses are within the range defined by the iobase and io limit registers. 1rw 0buncore serr enable (serren) 0 = no forwarding of error messages from secondary side to primary side that could result in an serr. 1 = err_cor, err_nonfatal, and err_fatal messages result in serr message when indivi dually enabled by the root control register. 0rw 0buncore parity error response enable (peren) controls whether or not the master data parity error bit in the secondary status register is set when the root port receives across the link (upstream) a read data completion poisoned tlp 0 = master data parity error bit in secondary status register can not be set. 1 = master data parity error bit in secondary status register can be set. b/d/f/type: 0/6/0/pci address offset: 3e?3fh reset value: 0000h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 186 datasheet, volume 2 2.10.25 pm_capid?power manage ment capabilities register b/d/f/type: 0/6/0/pci address offset: 80?83h reset value: c8039001h access: ro, ro-v size: 32 bits bit access reset value rst/ pwr description 31:27 ro 19h uncore pme support (pmes) this field indicates the power st ates in which this device may indicate pme wake using pci ex press messaging. d0, d3hot & d3cold. this device is not required to do anything to support d3hot & d3cold; it simply must report that those states are supported. refer to the pci power management 1.1 specification for encoding explanation and other power management details. 26 ro 0b uncore d2 power state support (d2pss) hardwired to 0 to indicate that the d2 power management state is not supported. 25 ro 0b uncore d1 power state support (d1pss) hardwired to 0 to indicate that the d1 power management state is not supported. 24:22 ro 000b uncore auxiliary current (auxc) hardwired to 0 to indicate that there are no 3.3vaux auxiliary current requirements. 21 ro 0b uncore device specific initialization (dsi) hardwired to 0 to indicate that sp ecial initialization of this device is not required before generic class device driver is to use it. 20 ro 0b uncore auxiliary power source (aps) hardwired to 0. 19 ro 0b uncore pme clock (pmeclk) hardwired to 0 to indicate this device does not support pme# generation. 18:16 ro 011b uncore pci pm cap version (pcipmcv) a value of 011b indicates that this function complies with revision 1.2 of the pci power management interface specification. --was previously hardwired to 02h to indicate there are 4 bytes of power management registers implemented and that this device complies with revision 1.1 of the pci power management interface specification. 15:8 ro-v 90h uncore pointer to next capability (pnc) this contains a pointer to the next item in the capabilities list. if msich (capl[0] @ 7fh) is 0, then the next item in the capabilities list is the messag e signaled interrupts (msi) capability at 90h. if msich (capl[0] @ 7fh) is 1, then the next item in the capabilities list is the pci express capability at a0h. 7:0 ro 01h uncore capability id (cid) value of 01h identifies this linke d list item (capability structure) as being for pci power management registers. datasheet, volume 2 187 processor configuration registers 2.10.26 pm_cs?power management control/status register b/d/f/type: 0/6/0/pci address offset: 84?87h reset value: 00000008h access: ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 ro 0b uncore pme status (pmests) this bit indicates that this device does not support pme# generation from d3cold. 14:13 ro 00b uncore data scale (dscale) this field indicates that this device does not support the power management data register. 12:9 ro 0h uncore data select (dsel) this field indicates that this device does not support the power management data register. 8rw 0buncore pme enable (pmee) this bit indicates that this device does not generate pme# assertion from any d-state. 0 = pme# generation not possible from any d state 1 = pme# generation enabled from any d state the setting of this bit has no effect on hardware. see pm_cap[15:11] 7:4 ro 0h reserved (rsvd) 3ro 1buncore no soft reset (nsr) when set to 1 this bit indicates that the device is transitioning from d3hot to d0 because the power state commands do not perform an internal reset. configuration context is preserved. upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits. when clear, the devices do not perform an internal reset upon transitioning from d3hot to d0 using software control of the power state bits. regardless of this bit the devices that transition from a d3hot to d0 by a system or bus segment reset will return to the device state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2ro 0h reserved (rsvd) processor configuration registers 188 datasheet, volume 2 1:0 rw 00b uncore power state (ps) this field indicates the current power state of this device and can be used to set the device into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 = d0 01 = d1 (not supported in this device.) 10 = d2 (not supported in this device.) 11 = d3 support of d3cold does not require any special action. while in the d3hot state, this device can only act as the target of pci configuration transactions (for power management control). this device also cannot generate interrupts or respond to mmr cycles in the d3 state. the device must return to the d0 state in order to be fully-functional. when the power state is other th an d0, the bridge will master abort (that is, not claim) any downstream cycles (with exception of type 0 configuration cycles). consequently, these unclaimed cycles will go down dmi and co me back up as unsupported requests, which the processor logs as master aborts in device 0 pcists[13] there is no additional hardware functionality required to support these power states. b/d/f/type: 0/6/0/pci address offset: 84?87h reset value: 00000008h access: ro, rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description datasheet, volume 2 189 processor configuration registers 2.10.27 ss_capid?subsystem id and vendor id capabilities register this capability is used to uniquely identify the subsystem where the pci device resides. because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. however, it is necessary because microsoft will test for its presence. 2.10.28 ss?subsystem id and su bsystem vendor id register system bios can be used as the mechanis m for loading the ssid/svid values. these values must be preserved through power management transitions and a hardware reset. b/d/f/type: 0/6/0/pci address offset: 88?8bh reset value: 0000800dh access: ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:8 ro 80h uncore pointer to next capability (pnc) this field contains a pointer to the next item in the capabilities list which is the pci power management capability. 7:0 ro 0dh uncore capability id (cid) value of 0dh identifies this linke d list item (capability structure) as being for ssid/ssvid regist ers in a pci-to-pci bridge. b/d/f/type: 0/6/0/pci address offset: 8c?8fh reset value: 00008086h access: rw-o size: 32 bits bit access reset value rst/ pwr description 31:16 rw-o 0000h uncore subsystem id (ssid) identifies the particular subsystem and is assigned by the vendor. 15:0 rw-o 8086h uncore subsystem vendor id (ssvid) identifies the manufacturer of th e subsystem and is the same as the vendor id which is assigned by the pci special interest group. processor configuration registers 190 datasheet, volume 2 2.10.29 msi_capid?message signal ed interrupts capability id register when a device supports msi it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. the reporting of the existence of this ca pability can be disabled by setting msich (capl[0] @ 7fh). in that case walking th is linked list will skip this capability and instead go directly from the pci pm capability to the pci express* capability. 2.10.30 mc?message control register system software can modify bits in this register, but the device is prohibited from doing so. if the device writes the same message multiple times, only one of those messages is ensured to be serviced. if all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. b/d/f/type: 0/6/0/pci address offset: 90?91h reset value: a005h access: ro size: 16 bits bit access reset value rst/ pwr description 15:8 ro a0h uncore pointer to next capability (pnc) this field contains a pointer to the next item in the capabilities list which is the pci express capability. 7:0 ro 05h uncore capability id (cid) value of 05h identifies this linke d list item (capability structure) as being for msi registers. b/d/f/type: 0/6/0/pci address offset: 92?93h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:8 ro 0h reserved (rsvd) 7ro 0buncore 64-bit address capable (b64ac) hardwired to 0 to indicate that the function does not implement the upper 32 bits of the message address register and is incapable of generating a 64-bit memory address. this may need to change in future implementations when addressable system memory exceeds the 32b/4 gb limit. datasheet, volume 2 191 processor configuration registers 2.10.31 ma?message address register 6:4 rw 000b uncore multiple message enable (mme) system software programs this field to indicate the actual number of messages allocated to th is device. this number will be equal to or less than the number actually requested. the encoding is the same as for the mmc field below. 3:1 ro 000b uncore multiple message capable (mmc) system software reads this field to determine the number of messages being requested by this device. 000 = 1 all of the following are reserv ed in this implementation: 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = reserved 111 = reserved 0rw 0buncore msi enable (msien) this bit controls the ability of this device to generate msis. 0 = msi will not be generated. 1 = msi will be generated when we receive pme messages. inta will not be generated and inta status (pcists1[3]) will not be set. b/d/f/type: 0/6/0/pci address offset: 94-97h reset value: 00000000h access: rw, ro size: 32 bits bit access reset value rst/ pwr description 31:2 rw 00000000h uncore message address (ma) used by system software to assign an msi address to the device. the device handles an msi by writing the padded contents of the md register to this address. 1:0 ro 00b uncore force dword align (fdwa) hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. b/d/f/type: 0/6/0/pci address offset: 92?93h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 192 datasheet, volume 2 2.10.32 md?message data register 2.10.33 peg_capl?pci express- g capability list register this register enumerates the pci express* capability structure. b/d/f/type: 0/6/0/pci address offset: 98?99h reset value: 0000h access: rw size: 16 bits bit access reset value rst/ pwr description 15:0 rw 0000h uncore message data (md) base message data pattern assigned by system software and used to handle an msi from the device. when the device must generate an interrupt request, it writes a 32-bit value to the memory addres s specified in the ma register. the upper 16 bits are always se t to 0. the lower 16 bits are supplied by this register. b/d/f/type: 0/6/0/pci address offset: a0?a1h reset value: 0010h access: ro size: 16 bits bit access reset value rst/ pwr description 15:8 ro 00h uncore pointer to next capability (pnc) this value terminates the capabi lities list. the virtual channel capability and any other pci expre ss specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within pci express extended configuration space. 7:0 ro 10h uncore capability id (cid) this field identifies this linked list item (capability structure) as being for pci express registers. datasheet, volume 2 193 processor configuration registers 2.10.34 peg_cap?pci express-g capabilities register this register indicates pci express* device capabilities. 2.10.35 dcap?device capabilities register this register indicates pci express* device capabilities. b/d/f/type: 0/6/0/pci address offset: a2?a3h reset value: 0142h access: ro, rw-o size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:14 ro 0h reserved (rsvd) 13:9 ro 00h uncore interrupt message number (imn) not applicable or imple mented. hardwired to 0. 8rw-o 1b uncore slot implemented (si) 0 = the pci express link associated with this port is connected to an integrated component or is disabled. 1 = the pci express link associated with this port is connected to a slot. bios requirement: this field must be initialized appropriately if a slot connection is not implemented. 7:4 ro 4h uncore device/port type (dpt) hardwired to 4h to indicate root port of pci express root complex. 3:0 ro 2h uncore pci express capability version (pciecv) hardwired to 2h to indicate compliance to the pci express capabilities register expansion ecn. b/d/f/type: 0/6/0/pci address offset: a4?a7h reset value: 00008000h access: ro, rw-o size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 ro 1b uncore role based error reporting (rber) this bit indicates that this devi ce implements the functionality defined in the error reporting ecn as required by the pci express 1.1 specification. 14:6 ro 0h reserved (rsvd) 5ro 0buncore extended tag field supported (etfs) hardwired to indicate support for 5-bit tags as a requestor. 4:3 ro 00b uncore phantom functions supported (pfs) not applicable or imple mented. hardwired to 0. 2:0 rw-o 000b uncore max payload size (mps) default indicates 128b max supported payload for transaction layer packets (tlp.). processor configuration registers 194 datasheet, volume 2 2.10.36 dctl?device control register this register provides control for pci express* device specific capabilities. the error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. th e reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclusively by root port command register. b/d/f/type: 0/6/0/pci address offset: a8?a9h reset value: 0000h access: ro, rw size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 ro 0h reserved (rsvd) 14:12 ro 000b uncore reserved for max read request size (mrrs) 11 ro 0b uncore reserved for enable no snoop (nse) 10:5 ro 0h reserved (rsvd) 4ro 0buncore reserved for enable relaxed ordering (roe) 3rw 0buncore unsupported request reporting enable (urre) when set, this bit allows sign aling err_nonfatal, err_fatal, or err_corr to the root control register when detecting an unmasked unsupported request (ur). an err_corr is signaled when an unmasked advisory non-fatal ur is received. an err_fatal or err_nonfatal is sent to the root control register when an uncorrectable non-advisory ur is received with the severity bit set in the uncorrectable error severity register. 2rw 0buncore fatal error reporting enable (fere) when set, this bit enables sign aling of err_fatal to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. 1rw 0buncore non-fatal error reporting enable (nere) when set, this bit enables sign aling of err_nonfatal to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. 0rw 0buncore correctable error reporting enable (cere) when set, this bit enables sign aling of err_corr to the root control register due to internally detected errors or error messages received across the link. other bits also control the full scope of related error reporting. datasheet, volume 2 195 processor configuration registers 2.10.37 dsts?device status register this register reflects status corresponding to controls in the device control register. the error reporting bits are in reference to errors detected by this device, not errors messages received across the link. b/d/f/type: 0/6/0/pci address offset: aa?abh reset value: 0000h access: ro, rw1c size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:6 ro 0h reserved (rsvd) 5ro 0buncore transactions pending (tp) 0 = all pending transactions (i ncluding completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used traffic classes). not applicable or impleme nted. hardwired to 0. 4ro 0h reserved (rsvd) 3rw1c 0b uncore unsupported request detected (urd) this bit indicates that the function received an unsupported request. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. 2rw1c 0b uncore fatal error detected (fed) this bit indicates status of fatal errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. 1rw1c 0b uncore non-fatal error detected (nfed) this bit indicates status of nonfatal errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi- function device, each function indicates status of errors as perceived by the respective function 0rw1c 0b uncore correctable error detected (ced) this bit indicates status of correctable errors detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. for a multi-function device, each function indicates status of errors as perceived by the respective function. processor configuration registers 196 datasheet, volume 2 2.10.38 lcap?link capa bilities register this register indicates pci express* device-specific capabilities. b/d/f/type: 0/6/0/pci address offset: ac?afh reset value: 0521cc42h access: ro, rw-o, ro-v, rw-ov size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:24 ro 05h uncore port number (pn) indicates the pci express port number for the given pci express link. matches the value in element self description[31:24]. the value if this field differs between root ports 2h = device 1 function 0 3h = device 1 function 1 4h = device 1 function 2 5h = device 6 function 0 23:22 ro 0h reserved (rsvd) 21 ro 1b uncore link bandwidth notification capability (lbnc) a value of 1b indicates support for the link bandwidth notification status and interrup t mechanisms. this capability is required for all root ports and switch downstream ports supporting links wider than x1 and/or multiple link speeds. this field is not applicable and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. devices that do not implement th e link bandwidth notification capability must hardwire this bit to 0b. 20 ro 0b uncore data link layer link active reporting capable (dlllarc) for a downstream port, this bit must be set to 1b if the component supports the optional capability of reporting the dl_active state of the data link control and management state machine. for a hot-plug capable downstream port (as indicated by the hot-plug capable field of the slot capabilities register), this bit must be set to 1b. for upstream ports and components that do not support this optional capability, this bit must be hardwired to 0b. note: pci express* hot-plug is not supported on the processor. 19 ro 0b uncore surprise down error reporting capable (sderc) for a downstream port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a surprise down error condition. for upstream ports and components that do not support this optional capability, this bit must be hardwired to 0b. 18 ro 0b uncore clock power management (cpm) a value of 1b in this bit indica tes that the component tolerates the removal of any reference clock(s) when the link is in the l1 and l2/3 ready link states. a value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these link states. this capability is applicable only in form factors that support "clock request" (clkreq#) capability. for a multi-function device, each function indicates its capability independently. power management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit. 17:15 ro 0h reserved (rsvd) datasheet, volume 2 197 processor configuration registers 14:12 ro-v 100b uncore l0s exit latency (l0selat ) this field indicates the length of time this port requires to complete the transition from l0s to l0. 000 = less than 64 ns 001 = 64 ns to less than 128 ns 010 = 128 ns to less than 256 ns 011 = 256 ns to less than 512 ns 100 = 512 ns to less than 1 us 101 = 1 us to less than 2 us 110 = 2 us ? 4 us 111 = more than 4 us the actual value of this field depends on the common clock configuration bit (lctl[6]) and the common and non-common clock l0s exit latency values in l0slat (offset 22ch) 11:10 rw-o 11b uncore active state link pm support (aslpms ) root port supports aspm l0s and l1. 9:4 rw-ov 04h uncore max link width (mlw): this field indicates the maximum number of lanes supported for this link. 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/pci address offset: ac?afh reset value: 0521cc42h access: ro, rw-o, ro-v, rw-ov size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 198 datasheet, volume 2 2.10.39 lctl?link control register this register allows control of pci express* link. b/d/f/type: 0/6/0/pci address offset: b0?b1h reset value: 0000h access: ro, rw, rw-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 rw 0b uncore link autonomous bandwidth interrupt enable (labie ) when set, this bit enables the generation of an interrupt to indicate that the link autonomous bandwidth status bit has been set. this bit is not applicab le and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. devices that do not implement th e link bandwidth notification capability must hardwire this bit to 0b. 10 rw 0b uncore link bandwidth management interrupt enable (lbmie ) link bandwidth management interrupt enable ? when set, this bit enables the generation of an in terrupt to indicate that the link bandwidth management status bit has been set. this bit is not applicab le and is reserved for endpoint devices, pci express to pci/pci-x bridges, and upstream ports of switches. 9rw 0buncore hardware autonomous width disable (hawd ) when set, this bit disables hardware from changing the link width for reasons other than attempting to correct unreliable link operation by reducing link width. devices that do not implemen t the ability autonomously to change link width are permitted to hardwire this bit to 0b. 8ro 0buncore enable clock power management (ecpm ) applicable only for form factors that support a "clock request" (clkreq#) mechanism, this en able functions as follows: 0 = clock power management is disabled and device must hold clkreq# signal low 1 = when this bit is set to 1 the device is permitted to use clkreq# signal to power manage link clock according to protocol defined in appropriate form factor specification. reset value of this field is 0b. components that do not support clock power management (as indicated by a 0b value in the clock power management bit of the link capabilities register) must hardwire this bit to 0b. 7rw 0buncore extended synch (es): 0 = standard fast training sequence (fts). 1 = forces the transmission of additional ordered sets when exiting the l0s state and when in the recovery state. this mode provides external devices (such as, logic analyzers) monitoring the link time to achi eve bit and symbol lock before the link enters l0 and resumes communication. this is a test mode only and may cause other undesired side effects such as buffer overflows or underruns. datasheet, volume 2 199 processor configuration registers 6rw 0buncore common clock configuration (ccc ) 0 = this component and the component at the opposite end of this link are operating with asynchronous reference clock. 1 = this component and the component at the opposite end of this link are operating with a distributed common reference clock. the state of this bit affects the l0s exit latency reported in lcap[14:12] and the n_fts value advertised during link training. see l0slat at offset 22ch. 5rw-v 0b uncore retrain link (rl ) 0 = normal operation. 1 = full link retraining is initiate d by directing the physical layer ltssm from l0, l0s, or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). 4rw 0buncore link disable (ld): 0 = normal operation 1 = link is disabled. forces the ltssm to transition to the disabled state (using recovery) from l0, l0s, or l1 states. link retraining happens automatically on 0 to 1 transition, just like when coming out of reset. writes to this bit are immediately reflected in the value read from the bit, regardless of actual link state. after clearing this bit, software must honor timing requirements defined in the pcie specification, section 6.6.1 with respect to the first configuration read following a conventional reset. 3ro 0buncore read completion boundary (rcb) hardwired to 0 to indicate 64 byte. 2ro 0h reserved (rsvd) 1:0 rw 00b uncore active state pm (aspm): this field controls the level of aspm (active state power management) supported on the given pci express link. b/d/f/type: 0/6/0/pci address offset: b0?b1h reset value: 0000h access: ro, rw, rw-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 200 datasheet, volume 2 2.10.40 lsts?link status register this register indicates pci express* link status. b/d/f/type: 0/6/0/pci address offset: b2?b3h reset value: 1001h access: rw1c, ro-v, ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15 rw1c 0b uncore link autonomous bandwidth status (labws) this bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through dl_down status, for reasons other than to attempt to correct unreliable link operation. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change. 14 rw1c 0b uncore link bandwidth management status (lbwms) this bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through dl_down status: a link retraining initiated by a write of 1b to the retrain link bit has completed. note: this bit is set following any write of 1b to the retrain link bit, including when the link is in the process of retraining for some other reason. hardware has autonomously changed link speed or width to attempt to correct unreliable link operation, either through an ltssm timeout or a higher level process. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change. 13 ro-v 0b uncore data link layer link active (optional) (dllla) this bit indicates the status of the data link control and management state machine. it returns a 1b to indicate the dl_active state, 0b otherwise. this bit must be implemented if the corresponding data link layer active capability bit is implemented. otherwise, this bit must be hardwired to 0b. 12 ro 1b uncore slot clock configuration (scc) 0 = the device uses an independent clock irrespective of the presence of a reference on the connector. 1 = the device uses the same ph ysical reference clock that the platform provides on the connector. 11 ro-v 0b uncore link training (ltrn) this bit indicates that the ph ysical layer ltssm is in the configuration or recovery state, or that 1b was written to the retrain link bit but link training has not yet begun. hardware clears this bit when the ltssm exits the configuration/recovery state once link training is complete. datasheet, volume 2 201 processor configuration registers 2.10.41 slotcap?slot capabilities register note: pci express* hot-plug is not supported on the processor. 10 ro 0h reserved (rsvd) 9:4 ro-v 00h uncore negotiated link width (nlw ) this field indicates negotiated link width. this field is valid only when the link is in the l0, l0s, or l1 states (after link width negotiation is successfully completed). 00h = reserved 01h = x1 02h = x2 04h = x4 08h = x8 10h = x16 all other encodings are reserved. 3:0 ro 0h uncore current link speed (cls) this field indicates the negotiated link speed of the given pci express link. the encoding is the binary valu e of the bit location in the supported link speeds vector (in the link capabilities 2 register) that corresponds to the current link speed. for example, a value of 0010b in this field indicates that the current link speed is that corres ponding to bit 2 in the supported link speeds vector, which is 5.0 gt/s. all other encodings are reserved. the value in this field is undefined when the link is not up. b/d/f/type: 0/6/0/pci address offset: b4?b7h reset value: 00040000h access: rw-o, ro size: 32 bits bit access reset value rst/ pwr description 31:19 rw-o 0000h uncore physical slot number (psn ) this field indicates the physical slot number attached to this port. bios requirement: this field must be initialized by bios to a value that assigns a slot number that is globally unique within the chassis. 18 ro 1b uncore no command completed support (nccs ) when set to 1b, this bit indicates that this slot does not generate software notification when an issued command is completed by the hot-plug controller. this bit is only permitted to be set to 1b if the hot-plug capable port is able to accept wr ites to all fields of the slot control register without delay between successive writes. 17 ro 0b uncore reserved for electromechanical interlock present (eip ) when set to 1b, this bit indicates that an electromechanical interlock is implemented on the chassis for this slot. b/d/f/type: 0/6/0/pci address offset: b2?b3h reset value: 1001h access: rw1c, ro-v, ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description processor configuration registers 202 datasheet, volume 2 16:15 rw-o 00b uncore slot power limit scale (spls ) this field specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x if this field is written, the link sends a set_slot_power_limit message. 14:7 rw-o 00h uncore slot power limit value (splv) in combination with the slot po wer limit scale value, specifies the upper limit on power supplied by slot. power limit (in watts) is calculated by multiplying the va lue in this field by the value in the slot power limit scale field. if this field is written, the link sends a set_slot_power_limit message. 6ro 0buncore reserved for hot-plug capable (hpc) when set to 1b, this bit indicates that this slot is capable of supporting hot-plug operations. 5ro 0buncore reserved for hot-plug surprise (hps) when set to 1b, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. this is a form factor specific capability. this bit is an indication to the operating syst em to allow for such removal without impacting continued software operation. 4ro 0buncore reserved for power indicator present (pip) when set to 1b, this bit indicates that a power indicator is electrically controlled by the chassis for this slot. 3ro 0buncore reserved for attention indicator present (aip) when set to 1b, this bit indicate s that an attention indicator is electrically controlled by the chassis. 2ro 0buncore reserved for mrl sensor present (msp) when set to 1b, this bit indicates that an mrl sensor is implemented on the chassis for this slot. 1ro 0buncore reserved for power controller present (pcp) when set to 1b, this bit indicates that a software programmable power controller is implemented fo r this slot/adapter (depending on form factor. ( 0ro 0buncore reserved for attention button present (abp) when set to 1b, this bit indicates that an attention button for this slot is electrically controlled by the chassis. b/d/f/type: 0/6/0/pci address offset: b4?b7h reset value: 00040000h access: rw-o, ro size: 32 bits bit access reset value rst/ pwr description datasheet, volume 2 203 processor configuration registers 2.10.42 slotctl?slot control register note: pci express* hot-plug is not supported on the processor. b/d/f/type: 0/6/0/pci address offset: b8?b9h reset value: 0000h access: ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description 15:13 ro 0h reserved (rsvd) 12 ro 0b uncore reserved for data link layer state changed enable (dllsce) if the data link layer link active capability is implemented, when set to 1b, this field enables software notification when data link layer link active field is changed. if the data link layer link active capability is not implemented, this bit is permitted to be read-only with a value of 0b. 11 ro 0b uncore reserved for electromechanical interlock control (eic) if an electromechanical interlock is implemented, a write of 1b to this field causes the state of the interlock to toggle. a write of 0b to this field has no effect. a read to this register always returns a 0. 10 ro 0b uncore reserved for power controller control (pcc) if a power controller is implemented, this field when written sets the power state of the slot per the defined encodings. reads of this field must reflect the value fr om the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. depending on the form factor, the power is turned on/off either to the slot or within the adapter. no te that in some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the power controller control setting. the defined encodings are: 0 = power on 1 = power off if the power controller implemented field in the slot capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined. 9:8 ro 00b uncore reserved power indicator control (pic) if a power indicator is implemented, writes to this field set the power indicator to the written state. reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00 = reserved 01 = on 10 = blink 11 = off if the power indicator present bit in the slot capabilities register is 0b, this field is permitted to be read-only with a value of 00b. processor configuration registers 204 datasheet, volume 2 7:6 ro 00b uncore reserved for attention indicator control (aic) if an attention indicator is implem ented, writes to this field set the attention indicator to the written state. reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write without waiting for the pr evious command to complete in which case the read value is undefined. if the indicator is electrically controlle d by chassis, the indicator is controlled directly by the downstream port through implementation specific mechanisms. 00 = reserved 01 = on 10 = blink 11 = off if the attention indicator present bit in the slot capabilities register is 0b, this field is permit ted to be read only with a value of 00b. 5 ro 0b uncore reserved for hot-plug interrupt enable (hpie) when set to 1b, this bit enables generation of an interrupt on enabled hot-plug events. reset value of this field is 0b. if the hot-plug capable field in the slot capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 4 ro 0b uncore reserved for command comple ted interrupt enable (cci) if command completed notification is supported (as indicated by no command completed support field of slot capabilities register), when set to 1b, this bit enables software notification when a hot-plug command is completed by the hot-plug controller. reset value of this field is 0b. if command completed notification is not supported, this bit must be hardwired to 0b. 3 ro 0b uncore presence detect changed enable (pdce) when set to 1b, this bit enables software notification on a presence detect changed event. 2 ro 0b uncore reserved for mrl sensor changed enable (msce) when set to 1b, this bit enables software notification on a mrl sensor changed event. reset value of this field is 0b. if the mrl sensor present field in the slot capabilities register is set to 0b, this bit is permitted to be read-only with a value of 0b. 1 ro 0b uncore reserved for power fault detected enable (pfde) when set to 1b, this bit enables software notification on a power fault event. reset value of this field is 0b. if power fault detection is not supp orted, this bit is permitted to be read-only with a value of 0b. 0 ro 0b uncore reserved for attention button pressed enable (abpe) when set to 1b, this bit enables software notification on an attention button pressed event. b/d/f/type: 0/6/0/pci address offset: b8?b9h reset value: 0000h access: ro size: 16 bits bios optimal default 0h bit access reset value rst/ pwr description datasheet, volume 2 205 processor configuration registers 2.10.43 slotsts?slot status register this is a pci express* slot related register. b/d/f/type: 0/6/0/pci address offset: ba?bbh reset value: 0000h access: ro, ro-v, rw1c size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:9 ro 0h reserved (rsvd) 8ro 0buncore reserved for data link layer state changed (dllsc) this bit is set when the value reported in the data link layer link active field of the link status register is changed. in response to a data link layer state changed event, software must read the data link layer link active field of the link status register to determine if the link is active befo re initiating configuration cycles to the hot plugged device. 7ro 0buncore reserved for electromechanical interlock status (eis) if an electromechanical interlock is implemented, this bit indicates the current status of the electromechanical interlock. 0 = electromechanical interlock disengaged 1 = electromechanical interlock engaged 6ro-v 0b uncore presence detect state (pds) in band presence detect state: 0 = slot empty 1 = card present in slot this bit indicates the presence of an adapter in the slot, reflected by the logical "or" of the physic al layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. the in-band presence detect mechanism requires that power be applied to an adapter for it s presence to be detected. consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism. 0 = slot empty 1 = card present in slot this register must be implemented on all downstream ports that implement slots. for downstream ports not connected to slots (where the slot implemented bit of the pci express capabilities register is 0b), this bit must return 1b. note: pci express* hot-plug is not supported on the processor. 5ro 0buncore reserved for mrl sensor state (mss) this register reports the status of the mrl sensor if it is implemented. 0 = mrl closed 1 = mrl open processor configuration registers 206 datasheet, volume 2 4ro 0buncore reserved for command completed (cc) if command completed notification is supported (as indicated by no command completed support field of slot capabilities register), this bit is set when a hot-plug command has completed and the hot-plug controller is ready to accept a subsequent command. the command completed status bit is set as an indication to host software that the hot-plug controller has processed the previous command and is ready to receive the next command; it provides no assurance that the action corresponding to the command is complete. if command completed notificatio n is not supported, this bit must be hardwired to 0b. note: pci express* hot-plug is not supported on the processor. 3rw1c 0b uncore presence detect changed (pdc) a pulse indication that the inba nd presence detect state has changed this bit is set when the value reported in presence detect state is changed. 2ro 0buncore reserved for mrl sensor changed (msc) if an mrl sensor is implemented, this bit is set when a mrl sensor state change is detected. if an mrl sensor is not implemented, this bit must not be set. 1ro 0buncore reserved for power fault detected (pfd) if a power controller that supp orts power fault detection is implemented, this bit is set when the power controller detects a power fault at this slot. note that, depending on hardware capability, it is possible that a po wer fault can be detected at any time, independent of the power controller control setting or the occupancy of the slot. if power fault detection is not supported, this bit must not be set. 0ro 0buncore reserved for attention button pressed (abp) if an attention button is implemen ted, this bit is set when the attention button is pressed. if an attention button is not supported, this bit must not be set. b/d/f/type: 0/6/0/pci address offset: ba?bbh reset value: 0000h access: ro, ro-v, rw1c size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description datasheet, volume 2 207 processor configuration registers 2.10.44 rctl?root control register this register allows control of pci expre ss* root complex specific parameters. the system error control bits in this regist er determine if corresponding serrs are generated when our device detects an error (reported in this device's device status register) or when an error message is received across the link. reporting of serr as controlled by these bits takes precedence over the serr enable in the pci command register. 2.10.45 lcap2?link capabilities 2 register b/d/f/type: 0/6/0/pci address offset: bc?bdh reset value: 0000h access: rw, ro size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:3 ro 0h reserved (rsvd) 2rw 0buncore system error on fatal error enable (sefee) this bit controls the root complex's response to fatal errors. 0 = no serr generated on receipt of fatal error. 1 = serr should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 1:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/pci address offset: cc?cfh reset value: 00000006h access: ro-v size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:1 ro-v 03h uncore supported link speeds vector (slsv): this field indicates the supported link speed(s) of the associated port. for each bit, a value of 1b indicates that the corresponding link speed is supported; otherwise, the link speed is not supported. bit definitions are: bit 1 = 2.5 gt/s bit 2 = 5.0 gt/s bit 3 = 8.0 gt/s bits 7:4 = reserved multi-function devices associated with an upstream port must report the same value in this field for all functions. dmi does not support this control register since it is gen3 register. 0ro 0h reserved (rsvd) processor configuration registers 208 datasheet, volume 2 2.11 pci device 6 extended configuration registers table 2-14. pci device 6 extended configuration register address map address offset symbol register name reset value access 0?103h rsvd reserved 0h ro 104?107h pvccap1 port vc capability register 1 00000000h ro 108?10bh pvccap2 port vc capability register 2 00000000h ro 10c?10dh pvcctl port vc control 0000h rw, ro 10e?10fh rsvd reserved 0h ro 110?113h vc0rcap vc0 resource capability 00000001h ro 114?117h vc0rctl vc0 resource control 800000ffh ro, rw 118?119h rsvd reserved 0h ro 11a?11bh vc0rsts vc0 resource status 0002h ro-v 11c?13fh rsvd reserved 0h ro 140?143h rcldech root complex link declaration enhanced 00010005h ro-v, ro 144?147h esd element self description 05000100h ro, rw-o 148?14fh rsvd reserved 0h ro 150?153h le1d link entry 1 description 00000000h ro, rw-o 154?157h rsvd reserved 0h ro 158?15bh le1a link entry 1 address 00000000h rw-o 15c?15fh le1ah link entry 1 address 00000000h rw-o 160?23fh rsvd reserved 0h ro 240?243h apicbase apic base address 00000000h rw 244?247h apiclimit apic base address limit 00000000h rw, 248?c33h rsvd reserved ? ? c34?c37h cmnrxerr common rx error register 00000000h rw1cs c38?d0bh rsvd reserved 0h ro d0c?d0fh pegtst pci express test modes 00000000h ro-fw, rw d10?d33h rsvd reserved 0h ro d34?d37h pegupdncfg peg upconfig/dnconfig control 0000001fh rw, rw1cs d38?d6bh rsvd reserved 0h ro d6c?d6fh bgfctl3 bgf control 3 400204e0h rw d70?dbfh rsvd reserved 0h ro dc0?dc3h eqpreset1_2 equalization preset 1/2 register 3400fbc0h rw dc4?dc7h eqpreset2_3_4 equalization preset 2/3/4 register 0037100ah rw dc8?dcbh rsvd reserved 0h ro dcc?dcfh eqpreset6_7 equalization preset 6/7 register 36200e06h rw dd0?dd7h rsvd reserved 0h ro dd8?ddbh eqcfg equalization configuration register 00000000h rw datasheet, volume 2 209 processor configuration registers 2.11.1 pvccap1?port vc capability register 1 this register describes the configuration of pci express* virtual channels associated with this port. 2.11.2 pvccap2?port vc capability register 2 this register describes the configuration of pci express* virtual channels associated with this port. b/d/f/type: 0/6/0/mmr address offset: 104?107h reset value: 00000000h access: ro size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:7 ro 0h reserved (rsvd) 6:4 ro 000b uncore low priority extended vc count (lpevcc) indicates the number of (extended) virtual channels in addition to the default vc belonging to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. th e value of 0 in this field implies strict vc arbitration. 3ro 0h reserved (rsvd) 2:0 ro 000b uncore extended vc count (evcc) indicates the number of (extended) virtual channels in addition to the default vc supported by the device. b/d/f/type: 0/6/0/mmr address offset: 108?10bh reset value: 00000000h access: ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 ro 00h uncore vc arbitration table offset (vcato): indicates the location of the vc arbitration table. this field contains the zero-based offset of the table in dqwords (16 bytes) from the base address of the virtual channel capability structure. a value of 0 indicates that the table is not present (due to fixed vc priority). 23:8 ro 0h reserved (rsvd) 7:0 ro 00h uncore reserved for vc arbitration capability (vcac): processor configuration registers 210 datasheet, volume 2 2.11.3 pvcctl?port vc control register 2.11.4 vc0rcap?vc0 resour ce capability register b/d/f/type: 0/6/0/mmr address offset: 10c?10dh reset value: 0000h access: rw, ro size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:4 ro 0h reserved (rsvd) 3:1 rw 000b uncore vc arbitration select (vcas) this field will be programmed by software to the only possible value as indicated in the vc ar bitration capability field. since there is no other vc supported than the default, this field is reserved. 0ro 0buncore reserved for load vc arbitration table (vcarb) used for software to update th e vc arbitration table when vc arbitration uses the vc arbitration table. as a vc arbitration table is never used by this component this field will never be used. b/d/f/type: 0/6/0/mmr address offset: 110?113h reset value: 00000001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for port arbitration table offset (pato) 23 ro 0h reserved (rsvd) 22:16 ro 00h uncore reserved for maximum time slots (mts) 15 ro 0b uncore reject snoop transactions (rsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request 14:8 ro 0h reserved (rsvd) datasheet, volume 2 211 processor configuration registers 7:0 ro 01h uncore port arbitration capability (pac) indicates types of port arbitration supported by the vc resource. this field is valid for all switch ports, root ports that support peer-to-peer traffic, and rcrbs, but not for pci express endpoint devices or root ports that do not support peer to peer traffic. each bit location within this fiel d corresponds to a port arbitration capability defined below. when more than one bit in this field is set, it indicates that the vc resource can be configured to provide different arbitration services. software selects among these capa bilities by writing to the port arbitration select field (see below). defined bit positions are: bit 0 non-configurable hardware-fixed arbitration scheme; such as, round robin (rr) bit 1 weighted round robin (wrr) arbitration with 32 phases bit 2 wrr arbitration with 64 phases bit 3 wrr arbitration with 128 phases bit 4 time-based wrr with 128 phases bit 5 wrr arbitration with 256 phases bits 6-7 reserved processor only supported arbitration indicates "non-configurable hardware-fixed arbitration scheme". b/d/f/type: 0/6/0/mmr address offset: 110?113h reset value: 00000001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description processor configuration registers 212 datasheet, volume 2 2.11.5 vc0rctl?vc0 reso urce control register this register controls the resources associated with pci express* virtual channel 0. b/d/f/type: 0/6/0/mmr address offset: 114?117h reset value: 800000ffh access: ro, rw size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31 ro 1b uncore vc0 enable (vc0e): for vc0 this is hardwired to 1 and read only as vc0 can never be disabled. 30:27 ro 0h reserved (rsvd) 26:24 ro 000b uncore vc0 id (vc0id): assigns a vc id to the vc resource. for vc0 this is hardwired to 0 and read only. 23:20 ro 0h reserved (rsvd) 19:17 rw 000b uncore port arbitration select (pas) port arbitration select ? this field configures the vc resource to provide a particular port arbitration service. this field is valid for rcrbs, root ports that support pe er to peer traffic, and switch ports, but not for pci express endpoint devices or root ports that do not support peer to peer traffic. the permissible value of this fi eld is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. this field does not affect the root port behavior. 16 ro 0h reserved (rsvd) 15:8 rw 00h uncore tc high vc0 map (tchvc0m): allow usage of high order tcs. bios should keep this field zeroed to allow usage of the reserved tc[3] for other purposes 7:1 rw 7fh uncore tc/vc0 map (tcvc0m) indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0ro 1buncore tc0/vc0 map (tc0vc0m) traffic class 0 is always routed to vc0. datasheet, volume 2 213 processor configuration registers 2.11.6 vc0rsts?vc0 reso urce status register this register reports the virtual channel specific status. 2.11.7 rcldech?root complex link declaration enhanced this capability declares links from this element (peg) to other elements of the root complex component to which it belongs. see pci express* specification for link/topology declaration requirements. b/d/f/type: 0/6/0/mmr address offset: 11a?11bh reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore vc0 negotiation pending (vc0np) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/6/0/mmr address offset: 140?143h reset value: 00010005h access: ro-v, ro size: 32 bits bit access reset value rst/ pwr description 31:20 ro 0h reserved (rsvd) 19:16 ro 1h uncore link declaration capability version (ldcv) hardwired to 1 to indicate comp liances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0005h uncore extended capability id (ecid) value of 0005 h identifies this linked list item (capability structure) as being for pci express link declaration capability. see corresponding egress port link declaration capability registers for diagram of link declaration topology. processor configuration registers 214 datasheet, volume 2 2.11.8 esd?element self description register this register provides information about the root complex element containing this link declaration capability. b/d/f/type: 0/6/0/mmr address offset: 144?147h reset value: 05000100h access: ro, rw-o size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:24 ro 05h uncore port number (pn) specifies the port number associated with this element with respect to the component that contains this element. note the value is in stantiation dependent: bdf 0.1.0 --> 02 bdf 0.1.1 --> 03 bdf 0.1.2 --> 04 bdf 0.6.0 --> 05 23:16 rw-o 00h uncore component id (cid) identifies the physical component that contains this root complex element. bios requirement: this field must be initialized according to guidelines in the pci express* isochronous/virtual channel support hardware programming specification (hps). 15:8 ro 01h uncore number of link entries (nle) indicates the number of link entries following the element self description. this field reports 1 (to egress port only). 7:4 ro 0h reserved (rsvd) 3:0 ro 0h uncore element type (et) indicates configuration space element. datasheet, volume 2 215 processor configuration registers 2.11.9 le1d?link entry 1 description register this register provides the first part of a li nk entry that declares an internal link to another root complex element. 2.11.10 le1a?link entry 1 address register this register provides the second part of a link entry that declares an internal link to another root complex element. b/d/f/type: 0/6/0/mmr address offset: 150?153h reset value: 00000000h access: ro, rw-o size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 ro 00h uncore target port number (tpn ) specifies the port number associated with the element targeted by this link entry (egress port). the target port number is with respect to the component that cont ains this element as specified by the target component id. 00h is the egress port (memory). 23:16 rw-o 00h uncore target component id (tcid ) identifies the physical or logica l component that is targeted by this link entry. bios requirement: this field must be in itialized according to guidelines in the pci express* isochronous/virtual channel support hardware programm ing specification (hps). 15:2 ro 0h reserved (rsvd) 1ro 0buncore link type (ltyp) indicates that the link points to memory-mapped space (for rcrb). the link address specifies the 64-bit base address of the target rcrb. 0rw-o 0b uncore link valid (lv) 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. bios should write "1' to this bit once it has programmed link entry 1 address (le1a) and while it writes the tcid in this register b/d/f/type: 0/6/0/mmr address offset: 158?15bh reset value: 00000000h access: rw-o size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31:12 rw-o 00000h uncore link address (la) memory mapped base address of the rcrb that is the target element (egress port) for this link entry. bios requirement: this field is inserted by bios such that it matches pxpepbar. 11:0 ro 0h reserved (rsvd) processor configuration registers 216 datasheet, volume 2 2.11.11 le1ah?link entry 1 address register this register provides the second part of a li nk entry that declares an internal link to another root complex element. 2.11.12 apicbase?apic base address register b/d/f/type: 0/6/0/mmr address offset: 15c?15fh reset value: 00000000h access: rw-o size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:0 rw-o 00h uncore link address (la ) memory mapped base address of the rcrb that is the target element (egress port) for this link entry. bios requirement: this field is inserted by bios such that it matches pxpepbar. b/d/f/type: 0/6/0/mmr address offset: 240?243h reset value: 00000000h access: rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:12 ro 0h reserved (rsvd) 11:4 rw 00h uncore apic base address (apicbase): bits 19:12 of the apic base bits 31:20 are assumed to be fech. bits 0:11 are don't care for address decode. address decoding to the apic range is done as: apic_base [31:12] a[31:12] apic_limit[31:12] 3:1 ro 0h reserved (rsvd) 0rw 0buncore apic range enable (apicre): enables the decode of the apic window. 0 = disable 1 = enable datasheet, volume 2 217 processor configuration registers 2.11.13 apiclimit?apic base address limit register 2.11.14 cmnrxerr?common rx error register b/d/f/type: 0/6/0/mmr address offset: 244?247h reset value: 00000000h access: rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:12 ro 0h reserved (rsvd) 11:4 rw 00h uncore apic base address (apiclimit): bits 19:12 of the apic limit bits 31:20 are assumed to be fech . bits 0:11 are don't care for address decode. address decoding to the apic range is done as: apic_base [31:12] a[31:12] apic_limit[31:12] 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/mmr address offset: c34?c37h reset value: 00000000h access: rw1cs size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:3 ro 0h reserved (rsvd) 2 rw1cs 0b powergood gen1/2 ufd framing error status (ufdframeerr): only applicable for gen1/gen2. when set, this field indicates that a framing error occurred in the link. (that is, dropped stp, dropped sdp, dropped end) 1:0 ro 0h reserved (rsvd) processor configuration registers 218 datasheet, volume 2 2.11.15 pegtst?pci expres s* test modes register 2.11.16 pegupdncfg?peg upconf ig/dnconfig control register this register allows software to dynamically limit the port width. the sequence to change width is: 1. write to this register the required width 2. set retrain link bit [5] in lctl register 3. wait till lsts.ltrn [11] is clear note: actual width may be lower due to card limitation. b/d/f/type: 0/6/0/mmr address offset: d0c?d0fh reset value: 00000000h access: ro-fw, rw size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:21 ro 0h reserved (rsvd) 20 ro-fw 0b uncore peg lane reversal strap status (lanerevsts) this register bit reflects the status of the peg lane reversal strap. the peglanereversal strap is mirrored in this register bit. 0 = peg lane is not reversed. 1 = peg lane is reversed. this bit is applicable only fo r function 0 in devices 1 and 6. note: lane reversal is done end-to-end regardless of bifurcation mode or not. 19:0 ro 0h reserved (rsvd) b/d/f/type: 0/6/0/mmr address offset: d34?d37h reset value: 0000001fh access: rw, rw1cs size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:7 ro 0h reserved (rsvd) 6rw 0buncore advertise upconfig capability (adupcfg) 0 = do not advertise upconfig support. 1 = set the upconfig capable bit to 1 in our transmitted ts2s during config.complete. 5:0 ro 0h reserved (rsvd) datasheet, volume 2 219 processor configuration registers 2.11.17 bgfctl3?bgf control 3 register b/d/f/type: 0/6/0/mmr address offset: d6c?d6fh reset value: 400204e0h access: rw size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31 rw 0b uncore fclock bubble enable (fben) this bit disable bubble generator on fclk side of bgf. 0 = disabled 1 = enabled. 30 rw 1b uncore lclock bubble enable (lben) this bit enable bubble generator on lclk side of bgf 0 = disabled 1 = enabled. bubble generation is disabled on slow side 29:18 ro 0h reserved (rsvd) 17:13 rw 10000b uncore slow ratio for gen 3 (srg3) this field defines the bgf slow ration for gen3 12:8 rw 00100b uncore bgf ratio delta for gen 3 (rdg3) this register defines the bgf ratio delta for gen 3. delta between the fast and slow clock multiplier 7:0 ro 0h reserved (rsvd) processor configuration registers 220 datasheet, volume 2 2.11.18 eqpreset1_2?equalizati on preset 1/2 register this register contains coefficients for preset 1 and 2. 2.11.19 eqpreset2_3_4?equalizati on preset 2/3/4 register this register contains coefficients for presets 2, 3, 4. b/d/f/type: 0/6/0/mmr address offset: dc0?dc3h reset value: 3400fbc0h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:30 ro 0h reserved (rsvd) 29:24 rw 34h uncore preset 2 cursor coefficient (cursor2) cursor coefficient for preset 2. 23:18 rw 00h uncore preset 2 precursor coefficient (precur2) precursor coefficient for preset 2. 17:6 ro 0h reserved (rsvd) 5:0 rw 00h uncore preset 1 precursor coefficient (precur1) precursor coefficient for preset 1. b/d/f/type: 0/6/0/mmr address offset: dc4?dc7h reset value: 0037100ah access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:12 ro 0h reserved (rsvd) 11:6 rw 00h uncore preset 3 precursor coefficient (precur3) precursor coefficient for preset 3. 5:0 rw 0ah uncore preset 2 postcursor coefficient (postcur2) postcursor coefficient for preset 2. datasheet, volume 2 221 processor configuration registers 2.11.20 eqpreset6_7?equaliz ation preset 6/7 register this register contains coefficients for preset 6 and 7. 2.11.21 eqcfg?equalization configuration register b/d/f/type: 0/6/0/mmr address offset: dcc?dcfh reset value: 36200e06h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:6 ro 0h reserved (rsvd) 5:0 rw 06h uncore preset 6 precursor coefficient (precur6): precursor coefficient for preset 6. b/d/f/type: 0/6/0/mmr address offset: dd8?ddbh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:2 ro 0h reserved (rsvd) 1rw 0 uncore disable margining (margindis) when set, it will disable tx ma rgining during polling.compliance and recovery. 0ro 0 reserved (rsvd) processor configuration registers 222 datasheet, volume 2 2.12 direct media interface base address registers (dmibar) table 2-15. dmibar register address map (s heet 1 of 2) address offset register symbol register name reset value access 0?3h dmivcech dmi virtual channel enhanced capability 04010002h ro 4?7h dmipvccap1 dmi port vc capability register 1 00000000h ro, rw-o 8?bh dmipvccap2 dmi port vc capability register 2 00000000h ro c?dh dmipvcctl dmi port vc control 0000h rw, ro e?fh rsvd reserved 0h ro 10?13h dmivc0rcap dmi vc0 resource capability 00000001h ro 14?17h dmivc0rctl dmi vc0 resource control 8000007fh ro, rw 18?19h rsvd reserved 0h ro 1a?1bh dmivc0rsts dmi vc0 resource status 0002h ro-v 1c?1fh dmivc1rcap dmi vc1 resource capability 00008001h ro 20?23h dmivc1rctl dmi vc1 resource control 01000000h ro, rw 24?25h rsvd reserved 0h ro 26?27h dmivc1rsts dmi vc1 resource status 0002h ro-v 28?2bh dmivcprcap dmi vcp resource capability 00000001h ro 2c?2fh dmivcprctl dmi vcp resource control 02000000h ro, rw 30?31h rsvd reserved 0h ro 32?33h dmivcprsts dmi vcp resource status 0002h ro-v 34?37h dmivcmrcap dmi vcm resource capability 00008000h ro 38?3bh dmivcmrctl dmi vcm resource control 07000080h rw, ro 3c?3dh rsvd reserved 0h ro 3e?3fh dmivcmrsts dmi vcm resource status 0002h ro-v 40?43h dmircldech dmi root complex link declaration 08010005h ro 44?47h dmiesd dmi element self description 01000202h ro, rw-o 48?4fh rsvd reserved 0h ro 50?53h dmile1d dmi link entry 1 description 00000000h rw-o, ro 54?57h rsvd reserved 0h ro 58?5bh dmile1a dmi link entry 1 address 00000000h rw-o 5c?5fh dmilue1a dmi link upper entry 1 address 00000000h rw-o 60?63h dmile2d dmi link entry 2 description 00000000h ro, rw-o 64?67h rsvd reserved 0h ro 68?6bh dmile2a dmi link entry 2 address 00000000h rw-o 6c?6fh rsvd reserved 00000000h rw-o 70?7fh rsvd reserved 0h ro 80?83h rsvd reserved 00010006h ro 84?87h lcap link capabilities 0001ac41h rw-o, ro, rw-ov 88?89h lctl link control 0000h rw, rw-v datasheet, volume 2 223 processor configuration registers 2.12.1 dmivcech?dmi virtual ch annel enhanced capability register this register indicates dmi virtual channel capabilities. 8a?8bh lsts dmi link status 0001h ro-v 8c?97h rsvd reserved 0h ro 98?99h lctl2 link control 2 0002h rws, rws-v 9a?9bh lsts2 link status 2 0000h ro-v 9c?d33h rsvd reserved 0h ro d34?d37h rsvd reserved 0000005fh rw, rw1cs table 2-15. dmibar register address map (sheet 2 of 2) address offset register symbol register name reset value access b/d/f/type: 0/0/0/dmibar address offset: 0?3h reset value: 04010002h access: ro size: 32 bits bit access reset value rst/ pwr description 31:20 ro 040h uncore pointer to next capability (pnc) this field contains the offset to the next pci express capability structure in the linked list of capabilities (link declaration capability). 19:16 ro 1h uncore pci express virtual channel capability version (pcievccv) hardwired to 1 to indicate comp liances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0002h uncore extended capability id (ecid) value of 0002h identifies this linked list item (capability structure) as being for pci express virtual channel registers. processor configuration registers 224 datasheet, volume 2 2.12.2 dmipvccap1?dmi port vc capability register 1 this register describes the configuration of pci express* virtual channels associated with this port. 2.12.3 dmipvccap2?dmi port vc capability register 2 this register describes the configuration of pci express* virtual channels associated with this port. b/d/f/type: 0/0/0/dmibar address offset: 4?7h reset value: 00000000h access: ro, rw-o size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:7 ro 0h reserved (rsvd) 6:4 ro 000b uncore low priority extended vc count (lpevcc) this field indicates the number of (extended) virtual channels in addition to the default vc belonging to the low-priority vc (lpvc) group that has the lowest priori ty with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 3ro 0h reserved (rsvd) 2:0 rw-o 000b uncore extended vc count (evcc) this field indicates the number of (extended) virtual channels in addition to the default vc supported by the device. b/d/f/type: 0/0/0/dmibar address offset: 8?bh reset value: 00000000h access: ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for vc arbitration table offset (vcato) 23:8 ro 0h reserved (rsvd) 7:0 ro 00h uncore reserved for vc arbitration capability (vcac) datasheet, volume 2 225 processor configuration registers 2.12.4 dmipvcctl?dmi port vc control register 2.12.5 dmivc0rcap?dmi vc0 re source capability register b/d/f/type: 0/0/0/dmibar address offset: c?dh reset value: 0000h access: rw, ro size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:4 ro 0h reserved (rsvd) 3:1 rw 000b uncore vc arbitration select (vcas) this field will be programmed by software to the only possible value as indicated in the vc arbitration capability field. the value 000b when written to th is field will indicate the vc arbitration scheme is hardware fixed (in the root complex). this field cannot be modified when more than one vc in the lpvc group is enabled. 000 = hardware fixed arbitration scheme such as round robin others = reserved see the pci express specification for more details. 0ro 0buncore reserved for load vc arbitration table (lvcat) b/d/f/type: 0/0/0/dmibar address offset: 10?13h reset value: 00000001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for port arbitration table offset (pato) 23 ro 0h reserved (rsvd) 22:16 ro 00h uncore reserved for maximum time slots (mts) 15 ro 0b uncore reject snoop transactions (rejsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = any transaction for which the no snoop attribute is applicable but is no t set within the tlp header will be rejected as an unsupported request. 14:8 ro 0h reserved (rsvd) 7:0 ro 01h uncore port arbitration capability (pac) having only bit 0 set indicates that the only supported arbitration scheme for this vc is non-co nfigurable hardware-fixed. processor configuration registers 226 datasheet, volume 2 2.12.6 dmivc0rctl?dmi vc0 re source control register this register controls the resources associated with pci express* virtual channel 0. b/d/f/type: 0/0/0/dmibar address offset: 14?17h reset value: 8000007fh access: ro, rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31 ro 1b uncore virtual channel 0 enable (vc0e) for vc0, this is hardwired to 1 and read only as vc0 can never be disabled. 30:27 ro 0h reserved (rsvd) 26:24 ro 000b uncore virtual channel 0 id (vc0id) this field assigns a vc id to the vc resource. for vc0, this is hardwired to 0 and read only. 23:20 ro 0h reserved (rsvd) 19:17 rw 000b uncore port arbitration select (pas) this field configures the vc resour ce to provide a particular port arbitration service. a valid value for this field is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. because only bit 0 of that field is asserted. this field will always be programmed to '1'. 16:8 ro 0h reserved (rsvd) 7ro 0buncore traffic class m / virtual channel 0 map (tcmvc0m) 6:1 rw 3fh uncore traffic class / virtual channel 0 map (tcvc0m) this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0ro 1buncore traffic class 0 / virtual channel 0 map (tc0vc0m) traffic class 0 is always routed to vc0. datasheet, volume 2 227 processor configuration registers 2.12.7 dmivc0rsts?dmi vc0 resource status register this register reports the virtual channel specific status. 2.12.8 dmivc1rcap?dmi vc1 re source capability register b/d/f/type: 0/0/0/dmibar address offset: 1a?1bh reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore virtual channel 0 negotiation pending (vc0np) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. bios requirement: before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 1c?1fh reset value: 00008001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for port arbitration table offset (pato) 23 ro 0h reserved (rsvd) 22:16 ro 00h uncore reserved for maximum time slots (mts) 15 ro 1b uncore reject snoop transactions (rejsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request. 14:8 ro 0h reserved (rsvd) 7:0 ro 01h uncore port arbitration capability (pac) having only bit 0 set indicates that the only supported arbitration scheme for this vc is non-co nfigurable hardware-fixed. processor configuration registers 228 datasheet, volume 2 2.12.9 dmivc1rctl?dmi vc1 re source control register this register controls the resources associated with pci express* virtual channel 1. b/d/f/type: 0/0/0/dmibar address offset: 20?23h reset value: 01000000h access: ro, rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31 rw 0b uncore virtual channel 1 enable (vc1e) 0 = virtual channel is disabled. 1 = virtual channel is enab led. see exceptions below. software must use the vc negotiation pending bit to check whether the vc negotiation is complete. when vc negotiation pending bit is cleared, a 1 read fr om this vc enable bit indicates that the vc is enabled (flow cont rol initialization is completed for the pci express port). a 0 read from this bit indicates that the virtual channel is currently disabled. bios requirement: 1. to enable a virtual channel, the vc enable bits for that virtual channel must be set in both components on a link. 2. to disable a virtual channel, the vc enable bits for that virtual channel must be cleare d in both components on a link. 3. software must ensure that no traffic is using a virtual channel at the time it is disabled. 4. software must fully disable a virtual channel in both components on a link before re-enabling the virtual channel. 30:27 ro 0h reserved (rsvd) 26:24 rw 001b uncore virtual channel 1 id (vc1id) assigns a vc id to the vc resource. assigned value must be non- zero. this field cannot be modi fied when the vc is already enabled. 23:20 ro 0h reserved (rsvd) 19:17 rw 000b uncore port arbitration select (pas) configures the vc resource to provide a particular port arbitration service. valid value for this field is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. 16:8 ro 0h reserved (rsvd) 7ro 0buncore traffic class m / virtual channel 1 (tcmvc1m) 6:1 rw 00h uncore traffic class / virtual channel 1 map (tcvc1m) this indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 6 is set in this field, tc6 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. bios requirement: program this field with the value 010001b, which maps tc1 and tc5 to vc1. 0ro 0buncore traffic class 0 / virtual channel 1 map (tc0vc1m) traffic class 0 is always routed to vc0. datasheet, volume 2 229 processor configuration registers 2.12.10 dmivc1rsts?dmi vc1 resource status register this register reports the virtual channel specific status. 2.12.11 dmivcprcap?dmi vcp re source capability register b/d/f/type: 0/0/0/dmibar address offset: 26?27h reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore virtual channel 1 negotiation pending (vc1np) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). software may use this bit when en abling or disabling the vc. this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 28?2bh reset value: 00000001h access: ro size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 00h uncore reserved for port arbitration table offset (pato) 23 ro 0h reserved (rsvd) 22:16 ro 00h uncore reserved for maximum time slots (mts) 15 ro 0b uncore reject snoop transactions (rejsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = any transaction for which the no snoop attribute is applicable but is no t set within the tlp header will be rejected as an unsupported request. 14:8 ro 0h reserved (rsvd) 7:0 ro 01h uncore reserved for port arbitration capability (pac) processor configuration registers 230 datasheet, volume 2 2.12.12 dmivcprctl?dmi vcp resource control register this register controls the resources associated with the dmi private channel (vcp). b/d/f/type: 0/0/0/dmibar address offset: 2c?2fh reset value: 02000000h access: ro, rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31 rw 0b uncore virtual channel private enable (vcpe) 0 = virtual channel is disabled. 1 = virtual channel is enab led. see exceptions below. software must use the vc negotiation pending bit to check whether the vc negotiation is complete. when vc negotiation pending bit is cleared, a 1 read fr om this vc enable bit indicates that the vc is enabled (flow cont rol initialization is completed for the pci express port). a 0 read from this bit indicates that the virtual channel is currently disabled. bios requirement: 1. to enable a virtual channel, the vc enable bits for that virtual channel must be set in both components on a link. 2. to disable a virtual channel, the vc enable bits for that virtual channel must be cleare d in both components on a link. 3. software must ensure that no traffic is using a virtual channel at the time it is disabled. 4. software must fully disable a virtual channel in both components on a link before re-enabling the virtual channel. 30:27 ro 0h reserved (rsvd) 26:24 rw 010b uncore virtual channel private id (vcpid) this field assigns a vc id to the vc resource. this field cannot be modified when the vc is already enabled. 23:8 ro 0h reserved (rsvd) 7ro 0buncore traffic class m / virtual channel private map (tcmvcpm) 6:1 rw 00h uncore traffic class / virtual cha nnel private map (tcvcpm) it is recommended that private tc6 (01000000b) is the only value that should be programmed into this field for vcp traffic which will be translated by a virtualization engine, and tc2 (00000010b) is the only value that should be programmed into this field for vcp traffic whic h will not be translated by a virtualization engine. this strategy can simplify debug and limit validation permutations. bios requirement: program this field with the value 100010b, which maps tc2 and tc6 to vcp. 0ro 0buncore tc0 vcp map (tc0vcpm) datasheet, volume 2 231 processor configuration registers 2.12.13 dmivcprsts?dmi vcp resource status register this register reports the virtual channel specific status. 2.12.14 dmivcmrcap?dmi vcm re source capability register b/d/f/type: 0/0/0/dmibar address offset: 32?33h reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore virtual channel private negotiation pending (vcpnp) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). software may use this bit when en abling or disabling the vc. this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 34?37h reset value: 00008000h access: ro size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 ro 1b uncore reject snoop transactions (rejsnpt) 0 = transactions with or without the no snoop bit set within the tlp header are allowed on the vc. 1 = any transaction for which the no snoop attribute is applicable but is no t set within the tlp header will be rejected as an unsupported request 14:0 ro 0h reserved (rsvd) processor configuration registers 232 datasheet, volume 2 2.12.15 dmivcmrctl?dmi vcm resource control register b/d/f/type: 0/0/0/dmibar address offset: 38?3bh reset value: 07000080h access: rw, ro size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31 rw 0b uncore virtual channel enable (vcmen) 0 = virtual channel is disabled. 1 = virtual channel is enable d. see exceptions below. software must use the vc negotiation pending bit to check whether the vc negotiation is complete. when vc negotiation pending bit is cleared, a 1 read fr om this vc enable bit indicates that the vc is enabled (flow cont rol initialization is completed for the pci express port). a 0 read from this bit indicates that the virtual channel is currently disabled. bios requirement: 1. to enable a virtual channel, the vc enable bits for that virtual channel must be set in both components on a link. 2. to disable a virtual channel, the vc enable bits for that virtual channel must be cleare d in both components on a link. 3. software must ensure that no traffic is using a virtual channel at the time it is disabled. 4. software must fully disable a virtual channel in both components on a link before re-enabling the virtual channel. 30:27 ro 0h reserved (rsvd) 26:24 rw 111b uncore virtual channel id (vcid) this field assigns a vc id to the vc resource. assigned value must be non-zero. this field cannot be modified when the vc is already enabled. 23:8 ro 0h reserved (rsvd) 7:0 ro 80h uncore traffic class/virtual channel map (tcvcmmap): this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. datasheet, volume 2 233 processor configuration registers 2.12.16 dmivcmrsts?dmi vcm resource status register 2.12.17 dmircldech?dmi root complex link declaration register this capability declares links from the respec tive element to other elements of the root complex component to which it belongs and to an element in another root complex component. see pci express* specification for link/topology declaration requirements. b/d/f/type: 0/0/0/dmibar address offset: 3e?3fh reset value: 0002h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:2 ro 0h reserved (rsvd) 1ro-v 1b uncore virtual channel negotiation pending (vcnegpnd) 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). software may use this bit when en abling or disabling the vc. this bit indicates the status of the process of flow control initialization. it is set by defaul t on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 40?43h reset value: 08010005h access: ro size: 32 bits bit access reset value rst/ pwr description 31:20 ro 080h uncore pointer to next capability (pnc) this field contains the offset to the next pci express capability structure in the linked list of capabilities (internal link control capability). 19:16 ro 1h uncore link declaration capability version (ldcv) hardwired to 1 to indicate comp liances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0005h uncore extended capability id (ecid) a value of 0005h identifies this linked list item (capability structure) as being for pci express link declaration capability. processor configuration registers 234 datasheet, volume 2 2.12.18 dmiesd?dmi element self description register this register provides information about the root complex element containing this link declaration capability. b/d/f/type: 0/0/0/dmibar address offset: 44?47h reset value: 01000202h access: ro, rw-o size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:24 ro 01h uncore port number (portnum) this field specifies th e port number associated with this element with respect to the component that contains this element. this port number value is utilized by the egress port of the component to provide arbitration to this root complex element. 23:16 rw-o 00h uncore component id (cid) this field identifies the physical component that contains this root complex element. bios requirement: this field must be initialized according to guidelines in the pci express* isochronous/virtual channel support hardware programming specification (hps). 15:8 ro 02h uncore number of link entries (nle) this field indicates the number of link entries following the element self description. this field reports 2 (one for mch egress port to main memory and one to egress port belonging to ich on other side of internal link). 7:4 ro 0h reserved (rsvd) 3:0 ro 2h uncore element type (etyp) this field indicates the type of the root complex element. a value of 2h represents an in ternal root complex link (dmi). datasheet, volume 2 235 processor configuration registers 2.12.19 dmile1d?dmi link en try 1 description register this register provides the first part of a link entry which declares an internal link to another root complex element. b/d/f/type: 0/0/0/dmibar address offset: 50?53h reset value: 00000000h access: rw-o, ro size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 rw-o 00h uncore target port number (tpn) this field specifies the port number associated with the element targeted by this link entry (egress port of pch). the target port number is with respect to the component that contains this element as specified by the target component id. this can be programmed by bios, but the reset value will likely be correct because the dmi rcrb in the pch will likely be associated with the default egress port for the pch meaning it will be assigned port number 0. 23:16 rw-o 00h uncore target component id (tcid) identifies the physical component that is targeted by this link entry. bios requirement: this field must be in itialized according to guidelines in the pci express* isochronous/virtual channel support hardware programm ing specification (hps). 15:2 ro 0h reserved (rsvd) 1ro 0buncore link type (ltyp) this bit indicates that the link points to memo ry-mapped space (for rcrb). the link address specifies the 64-bit base address of the target rcrb. 0rw-o 0b uncore link valid (lv) 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. processor configuration registers 236 datasheet, volume 2 2.12.20 dmile1a?dmi link entry 1 address register this register provides the second part of a li nk entry that declares an internal link to another root complex element. 2.12.21 dmilue1a?dmi link up per entry 1 address register this register provides the second part of a li nk entry that declares an internal link to another root complex element. b/d/f/type: 0/0/0/dmibar address offset: 58?5bh reset value: 00000000h access: rw-o size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31:12 rw-o 00000h uncore link address (la) memory mapped base address of the rcrb that is the target element (egress port of pch) for this link entry. 11:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 5c?5fh reset value: 00000000h access: rw-o size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:0 rw-o 00h uncore upper link address (ula) memory mapped base address of the rcrb that is the target element (egress port of pch) for this link entry. datasheet, volume 2 237 processor configuration registers 2.12.22 dmile2d?dmi link en try 2 description register this register provides the first part of a li nk entry that declares an internal link to another root complex element. b/d/f/type: 0/0/0/dmibar address offset: 60?63h reset value: 00000000h access: ro, rw-o size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:24 ro 00h uncore target port number (tpn) this field specifies the port number associated with the element targeted by this link entry (egress port). the target port number is with respect to the component that contains this element as specified by the target component id. 23:16 rw-o 00h uncore target component id (tcid) this field identifies the physical or logical component that is targeted by this link entry. bios requirement: this field must be initialized according to guidelines in the pci express* isochronous/virtual channel support hardware programm ing specification (hps). 15:2 ro 0h reserved (rsvd) 1ro 0buncore link type (ltyp) this field indicates that the link points to memory-mapped space (for rcrb). the link address specifies the 64-bit base address of the target rcrb. 0rw-o 0b uncore link valid (lv) 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. processor configuration registers 238 datasheet, volume 2 2.12.23 dmile2a?dmi link entry 2 address register this register provides the second part of a li nk entry that declares an internal link to another root complex element. 2.12.24 lcap?link capa bilities register this register indicates dmi specific capabilities. b/d/f/type: 0/0/0/dmibar address offset: 68?6bh reset value: 00000000h access: rw-o size: 32 bits bios optimal default 000h bit access reset value rst/ pwr description 31:12 rw-o 00000h uncore link address (la) memory mapped base address of the rcrb that is the target element (egress port) for this link entry. 11:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/dmibar address offset: 84?87h reset value: 0001ac41h access: rw-o, ro, rw-ov size: 32 bits bios optimal default 00002h bit access reset value rst/ pwr description 31:18 ro 0h reserved (rsvd) 17:15 rw-o 011b uncore l1 exit latency (l1selat) this field indicates th e length of time this port requires to complete the transition from l1 to l0. the value 011b indicates the range of 4 us to less than 8 us. 000 = less than 1s 001 = 1 s to less than 2 s 010 = 2 s to less than 4 s 011 = 4 s to less than 8 s 100 = 8 s to less than 16 s 101 = 16 s to less than 32 s 110 = 32 s-64 s 111 = more than 64 s both bytes of this register that co ntain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 rw-o 010b uncore l0s exit latency (l0selat) this field indicates th e length of time this port requires to complete the transition from l0s to l0. 000 = less than 64 ns 001 = 64 ns to less than 128 ns 010 = 128 ns to less than 256 ns 011 = 256 ns to less than 512 ns 100 = 512 ns to less than 1 s 101 = 1 s to less than 2 s 110 = 2 s-4 s 111 = more than 4 s datasheet, volume 2 239 processor configuration registers 2.12.25 lctl?link control register this register allows control of pci express* link. 11:10 ro 11b uncore active state link pm support (aslpms) l0s & l1 entry supported. 9:4 ro 04h uncore max link width (mlw) this field indicates the maximum number of lanes supported for this link. 3:0 rw-ov 0001b uncore max link speed (mls) this reset value reflects gen1. later the field may be changed by bios to allow gen2 subject to fuse enabled. defined encodings are: 0001b = 2.5 gt/s link speed supported 0010b = 5.0 gt/s and 2.5 gt/s link speeds supported b/d/f/type: 0/0/0/dmibar address offset: 84?87h reset value: 0001ac41h access: rw-o, ro, rw-ov size: 32 bits bios optimal default 00002h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/dmibar address offset: 88?89h reset value: 0000h access: rw, rw-v size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description 15:10 ro 0h reserved (rsvd) 9rw 0buncore hardware autonomous width disable (hawd) when set, this bit disables ha rdware from changing the link width for reasons other than attempting to correct unreliable link operation by reducing link width. devices that do not implemen t the ability autonomously to change link width are permitted to hardwire this bit to 0b. 8ro 0h reserved (rsvd) 7rw 0buncore extended synch (es) 0 = standard fast training sequence (fts). 1 = forces the transmission of additional ordered sets when exiting the l0s state and when in the recovery state. this mode provides external devices (such as, logic analyzers) monitoring the link time to achieve bit and symbol lock before the link enters l0 and resumes communication. this is a test mode only and may cause other undesired side effects such as buffer overflows or underruns. 6ro 0h reserved (rsvd) 5rw-v 0b uncore retrain link (rl) 0 = normal operation. 1 = full link retraining is initiate d by directing the physical layer ltssm from l0, l0s, or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). processor configuration registers 240 datasheet, volume 2 2.12.26 lsts?dmi link status register this register indicates dmi status. 4rw 0buncore link disable (ld) 0 = normal operation 1 = link is disabled. forces th e ltssm to transition to the disabled state (using recovery) from l0, l0s, or l1 states. link retraining happens automatically on 0 to 1 transition, just like when coming out of reset. writes to this bit are immediately reflected in the value read from the bit, regardless of actual link state. after clearing this bit, software must honor timing requirements defined in section 6.6.1 with re spect to the first configuration read following a conventional reset. 3ro 0buncore read completion boundary (rcb) hardwired to 0 to indicate 64 byte. 2ro 0h reserved (rsvd) 1:0 rw 00b uncore active state pm (aspm) this field controls the level of active state power management supported on the given link. 00 = disabled 01 = l0s entry supported 10 = reserved 11 = l0s and l1 entry supported b/d/f/type: 0/0/0/dmibar address offset: 88?89h reset value: 0000h access: rw, rw-v size: 16 bits bios optimal default 000h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/dmibar address offset: 8a?8bh reset value: 0001h access: ro-v size: 16 bits bios optimal default 00h bit access reset value rst/ pwr description 15:12 ro 0h reserved (rsvd) 11 ro-v 0b uncore link training (ltrn): this field indicates that the ph ysical layer ltssm is in the configuration or recovery state, or that 1b was written to the retrain link bit but link training has not yet begun. hardware clears this bit when the ltssm exits the configuration/recovery state once link training is complete. 10:0 ro 0h reserved (rsvd) datasheet, volume 2 241 processor configuration registers 2.12.27 lctl2?link control 2 register b/d/f/type: 0/0/0/dmibar address offset: 98?99h reset value: 0002h access: rws, rws-v size: 16 bits bit access reset value rst/ pwr description 15:12 rws 0000b powergood compliance de-emphasis (compliancedeemphasis) for 8 gt/s data rate: this fiel d sets the transmitter preset level in polling.compliance state if the entry o ccurred due to the enter compliance bit being 1b. the encodings are defined in pcie specification, section 4.2.3.2. for 5 gt/s data rate: this bit filed sets the de-emphasis level in polling.compliance state if th e entry occurred due to the enter compliance bit being 1b. 0001b = -3.5 db 0000b = -6 db when the link is operating at 2.5 gt/s, the setting of this bit has no effect. components that support only 2.5 gt/s speed are permitted to hardwire this bit to 0b. for a multi-function device associated with an upstream port, the bit in function 0 is of type rws, and only function 0 controls the component's link behavior. in all other functions of that device, this bit is of type rsvdp. the reset value of this bit is 0b. this bit is intended for debu g, compliance testing purposes. system firmware and software is allowed to modify this bit only during debug or compliance testing. 11 rws 0b powergood compliance sos (compsos) when set to 1b, the ltssm is required to send skp ordered sets periodically in betwee n the (modified) compliance patterns. for a multi-function device associated with an upstream port, the bit in function 0 is of type rws, and only function 0 controls the component's link behavior. in all other functions of that device, this bit is of type rsvdp. the reset value of this bit is 0b. comp onents that support only the 2.5 gt/s speed are permitted to hardwire this field to 0b. 10 rws 0b powergood enter modified compliance (entermodcompliance) when this bit is set to 1b, the device transmits modified compliance pattern if the lt ssm enters polling.compliance state. components that support onl y the 2.5 gt/s speed are permitted to hardwire this bit to 0b. reset value of this field is 0b. processor configuration registers 242 datasheet, volume 2 9:7 rws-v 000b powergood transmit margin (txmargin) this field controls the value of the non-deemphasized voltage level at the transmitter pins. this field is reset to 000b on entry to the ltssm polling.configuration substate (see pcie specification, chapter 4 for details of how the transmitter voltage level is determined in various states). 000 = normal operating range 001 = 800?1200 mv for full swing and 400?700 mv for half-swing 010 ? (n-1) = values must be monotonic with a non-zero slope. the value of n must be greater than 3 and less than 7. at least two of these must be below the normal operating range n = 200?400 mv for full-swing and 100?200 mv for half-swing n?111 = reserved reset value is 000b. components that support only the 2.5 gt/s speed are permitted to hardwire this bit to 0b. when operating in 5 gt/s mode with full swing, the de- emphasis ratio must be mainta ined within 1 db from the specification defined operational value (either -3.5 or -6 db). the processor supports the following values: 000 = normal operation (reset value); coefficients (cursor, precursor, postcursor) are at defined values 001 = coefficients are divided by 2 010 = coefficients are divided by 4 011 = coefficients are divided by 8 all other codes are reserved. the coefficients translate to 4 "level" values that are sent to the afe. note that tx marginin g has no effect on the levels if "bypass levels" are enabled. 6rws 0bpowergood selectable de-emphasis (selectabledeemphasis ) when the link is operating at 5 gt/s speed, selects the level of de-emphasis. encodings: 1b = -3.5 db 0b = -6 db when the link is operating at 2.5 gt/s speed, the setting of this bit has no effect. components that support only the 2.5 gt/s speed are permitted to hardwire this bit to 0b. note: for dmi this bit has no effect in functional mode as dmi is half-swing and will use -3.5 db whenever de-emphasis is enabled. b/d/f/type: 0/0/0/dmibar address offset: 98?99h reset value: 0002h access: rws, rws-v size: 16 bits bit access reset value rst/ pwr description datasheet, volume 2 243 processor configuration registers 2.12.28 lsts2?link status 2 register 5rws 0bpowergood hardware autonomous speed disable (hasd) when set to 1b this bit disabl es hardware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed. 4rws 0bpowergood enter compliance (ec) software is permitted to force a link to enter compliance mode at the speed indicated in the target link speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link. 3:0 rws 2h powergood target link speed (tls) for downstream ports, this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b = 2.5 gb/s target link speed 0010b = 5 gb/s target link speed all other encodings are reserved. if a value is written to this fi eld that does not correspond to a speed included in the supported link speeds field, the result is undefined. the reset value of this field is the highest link speed supported by the component (as reported in the supported link speeds field of the link capabilities re gister) unless the corresponding platform / form factor requires a different reset value. for both upstream and downstream ports, this field is used to set the target compliance mode speed when software is using the enter compliance bit to force a link into compliance mode. b/d/f/type: 0/0/0/dmibar address offset: 9a?9bh reset value: 0000h access: ro-v size: 16 bits bios optimal default 0000h bit access reset value rst/ pwr description 15:1 ro 0h reserved (rsvd) 0ro-v 0b uncore current de-emphasis level (curdelvl) when the link is operating at 5 gt/s speed, this reflects the level of de-emphasis. 1b = -3.5 db 0b = -6 db when the link is operating at 2. 5 gt/s speed, this bit is 0b. b/d/f/type: 0/0/0/dmibar address offset: 98?99h reset value: 0002h access: rws, rws-v size: 16 bits bit access reset value rst/ pwr description processor configuration registers 244 datasheet, volume 2 2.13 mchbar registers in memory controller?channel 0 registers table 2-16. mchbar regi sters in memory controller ? channel 0 register address map address offset register symbol register name reset value access 0?3fffh rsvd reserved 0h ro 4000?4003h tc_dbp_c0 timing of ddr ? bin parameters 00146666h rw-l 4004?4007h tc_rap_c0 timing of ddr ? regular access parameters 86104344h rw-l 4008?4027h rsvd reserved ? ? 4028?402bh sc_io_late ncy_c0 io latency configuration 000e0000h rw-l 402c?409fh rsvd reserved ? ? 40a0?40a3h pm_pdwn_c onfig_c0 power-down configuration register 00000000h rw-l 40a4?40b3h rsvd reserved ? ? 40bc?40c7h rsvd reserved 0h ro 40c8?40cbh eccerrlog0 _c0 ecc error log 0 00000000h ros-v 40cc?40cfh eccerrlog1 _c0 ecc error log 1 00000000h ros-v 40d0?4293h rsvd reserved ? ? 4294?4297h tc_rfp_c0 refresh parameters 0000980fh rw-l 4298?429bh tc_rftp_c0 refresh timing parameters 46b41004h rw-l 429c?438fh rsvd reserved ? ? datasheet, volume 2 245 processor configuration registers 2.13.1 tc_dbp_c0?timing of ddr ? bin parameters register this register defines the bin timing paramete rs for safe logic ? trcd, trp, tcl, twcl and tras. b/d/f/type: 0/0/0/mchbar mc0 address offset: 4000?4003h reset value: 00146666h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 0h reserved (rsvd) 23:16 rw-l 14h uncore tras in dclk cycles (tras) minimum act to pre timing ra nge is 10 to 40 dclk cycles 15:12 rw-l 6h uncore write cas latency in dclk cycles (twcl) delay from cas wr command to data valid on ddr pins. range is 5?15. the value 5 should not be programmed if the dec_wrd bit in tc_rwp register is set. 11:8 rw-l 6h uncore cas latency in dclk cycles (tcl) this field is the delay from cas command to data out of ddr pins. this does not define the sample po int in the io. this is defined by training in round-trip register and other registers, because this is also affected by board delays. delay from cas command to data out of ddr pins. range is 5? 15. notes: 1. this does not define the samp le point in the io. this is defined by training in round-trip register and other registers, because this is also affected by board delays. 2. the range of 12?15 is not yet defined by jedec, will be tested only when such definition will exist. 7:4 rw-l 6h uncore trp in dclk cycles (trp) pre to act same bank delay range is 4?15 dclk cycles 3:0 rw-l 6h uncore trcd in dclk cycles (trcd) act to cas (rd or wr) same bank delay trcd range is between 4 and 15. processor configuration registers 246 datasheet, volume 2 2.13.2 tc_rap_c0?timing of ddr ? regular access parameters register thie register is for the regular ti ming parameters in dclk cycles. b/d/f/type: 0/0/0/mchbar mc0 address offset: 4004?4007h reset value: 86104344h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:30 rw-l 10b uncore 1n 2n or 3n selection (cmd_stretch) this field defines the operation mode of the command. 00 = n operation 10 = 2n operation 11 = 3n operation 29 rw-l 0b uncore command 3-state options (cmd_3st) this bit defines when command & address bus is driving. 0 = drive when channel is active. tri-stated when all ranks are in cke-off or when memory is in sr or deeper. 1 = command bus is always driving. when no new valid command is driven, previous command & address is driven 28:24 rw-l 06h uncore twr in dclk cycles (twr) write recovery time. the range is 5 to 16 dclk cycles. 23:16 rw-l 10h uncore tfaw in dclk cycles (tfaw) four-activate window is the time frame in which maximum of 4 act commands to the same rank are allowed. the minimum value is 4*trrd, whereas the maximum value is 63 dclk cycles. 15:12 rw-l 4h uncore twtr in dclk cycles (twtr) delay from internal wr transactio n to internal rd transaction. the minimum delay is 4 dclk cycles, whereas the maximum delay is 8 dclk cycles. 11:8 rw-l 3h uncore tcke in dclk cycles (tcke) cke minimum pulse width in dclk cycles. the minimum value is 3 dclk cycles, whereas the maximum value is the actual value of txp. 7:4 rw-l 4h uncore trtp in dclk cycles (trtp) minimum delay from cas-rd to pre. the minimum delay is 4 dclk cycles, whereas the maximum delay is 8 dclk cycles. 3:0 rw-l 4h uncore trrd in dclk cycles (trrd) trrd is the minimum delay between two act commands targeted to different banks in the same rank. the minimum delay is 4 dclk cycles, whereas the maximum delay is 7 cycles. datasheet, volume 2 247 processor configuration registers 2.13.3 sc_io_latency_c0?io la tency configuration register this register identifies the i/o latency per rank, and i/o compensation (global). 2.13.4 tc_srftp_c0?self refresh timing parameters register this register is for the self-refresh timing parameters. b/d/f/type: 0/0/0/mchbar mc0 address offset: 4028?402bh reset value: 000e0000h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:22 ro 0h reserved (rsvd) 21:16 rw-l 0eh uncore round trip ? i/o compensation (rt_iocomp) 15:12 rw-l 0h uncore io latency rank 1 dimm 1 (iolat_r1d1) 11:8 rw-l 0h uncore io latency rank 0 dimm 1 (iolat_r0d1) 7:4 rw-l 0h uncore io latency rank 1 dimm 0 (iolat_r1d0) 3:0 rw-l 0h uncore io latency rank 0 dimm 0 (iolat_r0d0) b/d/f/type: 0/0/0/mchbar mc0 address offset: 42a4?42a7h reset value: 0100b200h access: rw-l size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:28 rw-l 0h uncore (tmod) this field is the time between mrs command and any other command in dclk cycles. actual value is 8 + programmed-value. for example, when programming 4 in the field, tmod value is actually 12 dclk cycles 27:26 ro 0h reserved (rsvd) 25:16 rw-l 100h uncore (tzqoper) defines the period required for zqcl after sr exit 15:12 rw-l bh uncore (txs_offset) delay from sr exit to the first ddr command txs = trfc+10ns. setup of txs_offset is # of cycles for 10 ns. range is between 3 and 11 dclk cycles. 11:0 rw-l 200h uncore (txsdll) delay between ddr sr exit and the first command that requires data rd/wr from ddr is in the range of 128 to 1024 dclk cycles, though all jedec ddrs assume 512 dclk cycles processor configuration registers 248 datasheet, volume 2 2.13.5 pm_pdwn_config_c0?p ower-down configuration register this register defines the power-down (cke-off) operation ? power-down mode, idle timer and global / per rank decision. b/d/f/type: 0/0/0/mchbar mc0 address offset: 40b0?40b3h reset value: 00000000h access: rw-l size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:13 ro 0h reserved (rsvd) 12 rw-l 0b uncore global power-down (glpdn) 1 = when this bit is set, the power-down decision is global for channel. 0 = when this bit is clear, a separate decision is taken for each rank. 11:8 rw-l 0h uncore power-down mode (pdwn_mode) selects the mode of power-down: 0h = no power-down 1h = apd 2h = ppd 3h = apd+ppd 4h = reserved 5h = reserved 6h = ppd_dlloff 7h = apd+ppd_dlloff 8h?fh = reserved note: when selecting dll-off or apd-dll off, dimm mr0 register bit 12 (ppd) must equal 0. note: when selecting apd, ppd or apd-ppd dimm mr0 register bit 12 (ppd) must equal 1. the value 0x0 (no power-down) is a don't care. 7:0 rw-l 00h uncore power-down idle timer (pdwn_idle_counter) this field defines the rank idle period in dclk cycles that causes power-down entrance. datasheet, volume 2 249 processor configuration registers 2.13.6 eccerrlog0_c0?ecc error log 0 register b/d/f/type: 0/0/0/mchbar mc0 address offset: 40c8?40cbh reset value: 00000000h access: ros-v size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:29 ros-v 000b powergood error bank (errbank) this field holds the bank address of the read transaction that had the ecc error. 28:27 ros-v 00b powergood error rank (errrank) this field holds the rank id of the read transaction that had the ecc error. 26:24 ros-v 000b powergood error chunk (errchunk) holds the chunk number of the error stored in the register. 23:16 ros-v 00h powergood error syndrome (errsynd) this field contains the error syndrome. a value of ffh indicates that the error is due to poisoning. 15:2 ro 0h reserved (rsvd) 1 ros-v 0b powergood uncorrectable error status (merrsts) this bit is set when an uncorrect able multiple-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. 0 ros-v 0b powergood correctable error status (cerrsts) this bit is set when a correctable single-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. a multiple bit error that occurs af ter this bit is set will override the address/error syndrome information. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. processor configuration registers 250 datasheet, volume 2 2.13.7 eccerrlog1_c0?ecc error log 1 register 2.13.8 tc_rfp_c0?refresh parameters register this register provides the refresh parameters. b/d/f/type: 0/0/0/mchbar mc0 address offset: 40cc?40cfh reset value: 00000000h access: ros-v size: 32 bits bit access reset value rst/ pwr description 31:16 ros-v 0000h powergood error column (errcol) this field holds the dram column address of the read transaction that had the ecc error. 15:0 ros-v 0000h powergood error row (errrow) this field holds the dram row (page) address of the read transaction that had the ecc error. b/d/f/type: 0/0/0/mchbar mc0 address offset: 4294?4297h reset value: 0000980fh access: rw-l size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:18 ro 0h reserved (rsvd) 17:16 rw-l 00b uncore double refresh control (d ouble_refresh_control) this field will allow the double self refr esh enable/disable. 00 = double refresh rate when dram is warm/hot. 01 = force double self refresh regardless of temperature. 10 = disable double self refresh regardless of temperature. 11 = reserved 15:12 rw-l 9h uncore refresh panic wm (refresh_panic_wm) trefi count level in which the refres h priority is panic (default is 9) it is recommended to set the panic wm at least to 9, in order to use the maximum no-refresh period possible. 11:8 rw-l 8h uncore refresh high priority wm (refresh_hp_wm) trefi count level that turns the refresh priority to high (default is 8) 7:0 rw-l 0fh uncore rank idle timer for opportunistic refresh (oref_ri) rank idle period that defines an opportunity for refresh, in dclk cycles datasheet, volume 2 251 processor configuration registers 2.13.9 tc_rftp_c0?refresh ti ming parameters register this register provides the refresh timing parameters. b/d/f/type: 0/0/0/mchbar mc0 address offset: 4298?429bh reset value: 46b41004h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:25 rw-l 23h uncore 9 * trefi period of minimum between 9*trefi and tras maximum (normally 70 us) in 1024 * dclk cycles (default is 35h). 24:16 rw-l 0b4h uncore refresh execution time (trfc) time of refresh ? from beginning of refresh until next act or refresh is allowed (in dclk cycles, default is 180h). 15:0 rw-l 1004h uncore trefi period in dclk cycles (trefi) this field defines the average period between refreshes, and the rate that trefi counter is incremented (in dclk cycles, default is 4100h). processor configuration registers 252 datasheet, volume 2 2.14 mchbar registers in memory controller ? channel 1 2.14.1 tc_dbp_c1?timing of ddr ? bin parameters register this register defines the bin timing paramete rs for safe logic ? trcd, trp, tcl, twcl and tras. table 2-17. mchbar regi sters in memory controller ? channel 1 register address map address register symbol register name reset value access 0?43ffh rsvd reserved 0h ro 4400?4403h tc_dbp_c1 timing of ddr ? bin parameters 00146666h rw-l 4404?4407h tc_rap_c1 timing of ddr ? regular access parameters 86104344h rw-l 4408?4427h rsvd reserved ? ? 4428?442bh sc_io_latency_ c1 io latency configuration 000e0000h rw-l 442c?44afh rsvd reserved ? ? 44b0?44b3h pm_pdwn_config _c1 power-down configuration register 00000000h rw-l 44bc?44c7h rsvd reserved 0h ro 44c8?44cbh eccerrlog0_c1 ecc error log 0 00000000h ros-v 44cc?44cfh eccerrlog1_c1 ecc error log 1 00000000h ros-v 44d0?4693h rsvd reserved ? ? 4694?4697h tc_rfp_c1 refresh parameters 0000980fh rw-l 4698?469bh tc_rftp_c1 refresh timing parameters 46b41004h rw-l 469c?469fh rsvd reserved 00000000h rw-l 46a0?46a3h rsvd reserved 00000000h rw-l 46a4?46a7h tc_srftp_c1 self refresh timing parameters 0100b200h rw-l 46a8?478fh rsvd reserved ? ? b/d/f/type: 0/0/0/mchbar mc1 address offset: 4400?4403h reset value: 00146666h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 0h reserved (rsvd) 23:16 rw-l 14h uncore tras in dclk cycles (tras) minimum act to pre timing range is 10 to 40 dclk cycles. 15:12 rw-l 6h uncore write cas latency in dclk cycles (twcl) delay from cas wr command to data valid on ddr pins. range is 5?15. the value 5 should not be programmed if the dec_wrd bit in tc_rwp register is set. datasheet, volume 2 253 processor configuration registers 2.14.2 tc_rap_c1?timing of ddr ? regular access parameters register this register provides the regular timing parameters in dclk cycles. 11:8 rw-l 6h uncore cas latency in dclk cycles (tcl) delay from cas command to data out of ddr pins. this does not define the sample point in the i/o. this is defined by training in round-trip register and other registers, because this is also affected by board delays delay from cas command to data out of ddr pins. range is 5? 15. note: this does not define the samp le point in the io. this is defined by training in round-trip register and other registers, because this is also affected by board delays. note: the range of 12?15 is not yet defined by jedec, will be tested only when such definition will exist. 7:4 rw-l 6h uncore trp in dclk cycles (trp) pre to act same bank delay range is 4?15 dclk cycles 3:0 rw-l 6h uncore trcd in dclk cycles (trcd) act to cas (rd or wr) same bank delay trcd range is between 4 and 15. b/d/f/type: 0/0/0/mchbar mc1 address offset: 4400?4403h reset value: 00146666h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/mchbar mc1 address offset: 4404?4407h reset value: 86104344h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:30 rw-l 10b uncore 1n 2n or 3n selection (cmd_stretch) this field defines the operation mode of the command 00 = 1n operation 10 = 2n operation 11 = 3n operation 29 rw-l 0b uncore command 3-state options (cmd_3st) this bit defines when command & address bus is driving. 0 = drive when channel is active. tri-stated when all ranks are in cke-off or when memory is in sr or deeper. 1 = command bus is always driving. when no new valid command is driven, previous command & address is driven 28:24 rw-l 06h uncore twr in dclk cycles (twr) write recovery time. the range is 5 to 16 dclk cycles. 23:16 rw-l 10h uncore tfaw in dclk cycles (tfaw) four-activate window is the time frame in which maximum of 4 act commands to the same rank are allowed. the minimum value is 4*trrd, whereas the maximum value is 63 dclk cycles. processor configuration registers 254 datasheet, volume 2 2.14.3 sc_io_latency_c1?io la tency configuration register this register identifies the i/o latency per rank, and i/o compensation (global). 15:12 rw-l 4h uncore twtr in dclk cycles (twtr) delay from internal wr transactio n to internal rd transaction. the minimum delay is 4 dclk cycles, whereas the maximum delay is 8 dclk cycles. 11:8 rw-l 3h uncore tcke in dclk cycles (tcke) cke minimum pulse width in dclk cycles. the minimum value is 3 dclk cycles, whereas the maximum value is the actual value of txp. 7:4 rw-l 4h uncore trtp in dclk cycles (trtp) minimum delay from cas-rd to pre. the minimum delay is 4 dclk cycles, whereas the maximum delay is 8 dclk cycles. 3:0 rw-l 4h uncore trrd in dclk cycles (trrd) trrd is the minimum delay between two act commands targeted to different banks in the same rank. the minimum delay is 4 dclk cycles, whereas the maximum delay is 7 cycles. b/d/f/type: 0/0/0/mchbar mc1 address offset: 4404?4407h reset value: 86104344h access: rw-l size: 32 bits bit access reset value rst/ pwr description b/d/f/type: 0/0/0/mchbar mc1 address offset: 4428?442bh reset value: 000e0000h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:22 ro 0h reserved (rsvd) 21:16 rw-l 0eh uncore round trip ? i/o compensation (rt_iocomp) 15:12 rw-l 0h uncore io latency rank 1 dimm 1 (iolat_r1d1) 11:8 rw-l 0h uncore io latency rank 0 dimm 1 (iolat_r0d1) 7:4 rw-l 0h uncore io latency rank 1 dimm 0 (iolat_r1d0) 3:0 rw-l 0h uncore io latency rank 0 dimm 0 (iolat_r0d0) datasheet, volume 2 255 processor configuration registers 2.14.4 pm_pdwn_config_c1?po wer-down configuration register this register defines the power-down (cke -off) operation ? power-down mode, idle timer and global / per rank decision. b/d/f/type: 0/0/0/mchbar mc1 address offset: 44b0?44b3h reset value: 00000000h access: rw-l size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:13 ro 0h reserved (rsvd) 12 rw-l 0b uncore global power-down (glpdn) 1 = power-down decision is global for channel. 0 = separate decision is taken for each rank. 11:8 rw-l 0h uncore power-down mode (pdwn_mode) selects the mode of power-down: 0h = no power-down 1h = apd 2h = ppd 3h = apd+ppd 4h = reserved 5h = reserved 6h = ppd_dlloff 7h =: apd+ppd_dlloff 8h?fh = reserved note: when selecting dll-off or apd-dll off, dimm mr0 register bit 12 (ppd) must equal 0. note: when selecting apd, ppd or apd-ppd dimm mr0 register bit 12 (ppd) must equal 1. the value 0h (no power-down) is a don't care. 7:0 rw-l 00h uncore power-down idle timer (pdwn_idle_counter) this field defines the rank idle pe riod in dclk cycles that causes power-down entrance. processor configuration registers 256 datasheet, volume 2 2.14.5 eccerrlog0_c1?ecc error log 0 register b/d/f/type: 0/0/0/mchbar mc1 address offset: 44c8?44cbh reset value: 00000000h access: ros-v size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:29 ros-v 000b powergood error bank (errbank) this field holds the bank address of the read transaction that had the ecc error. 28:27 ros-v 00b powergood error rank (errrank) this field holds the rank id of the read transaction that had the ecc error. 26:24 ros-v 000b powergood error chunk (errchunk) holds the chunk number of the error stored in the register. 23:16 ros-v 00h powergood error syndrome (errsynd) this field contains the error syndrome. a value of ffh indicates that the error is due to poisoning. 15:2 ro 0h reserved (rsvd) 1ros-v 0b powergood uncorrectable error status (merrsts) this bit is set when an uncorrect able multiple-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. 0ros-v 0b powergood correctable error status (cerrsts) this bit is set when a correctable single-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. a multiple bit error that occurs after this bit is set will override the address/error syndrome information. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. datasheet, volume 2 257 processor configuration registers 2.14.6 eccerrlog1_c1?ecc error log 1 register 2.14.7 tc_rfp_c1?refresh parameters register this register provides refresh parameters. b/d/f/type: 0/0/0/mchbar mc1 address offset: 44cc?44cfh reset value: 00000000h access: ros-v size: 32 bits bit access reset value rst/ pwr description 31:16 ros-v 0000h powergood error column (errcol) this field holds the dram column address of the read transaction that had the ecc error. 15:0 ros-v 0000h powergood error row (errrow) this field holds the dram row (page) address of the read transaction that had the ecc error. b/d/f/type: 0/0/0/mchbar mc1 address offset: 4694?4697h reset value: 0000980fh access: rw-l size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:18 ro 0h reserved (rsvd) 17:16 rw-l 00b uncore double refresh control (double_refresh_control) this field will allow the double self refresh enable/disable. 00 = double refresh rate when dram is warm/hot. 01 = force double self refresh regardless of temperature. 10 = disable double self refresh regardless of temperature. 11 = reserved 15:12 rw-l 9h uncore refresh panic wm (refresh_panic_wm) trefi count level in which the refresh priority is panic (default is 9) it is recommended to set the panic wm at least to 9, in order to use the maximum no-refresh period possible 11:8 rw-l 8h uncore refresh high priority wm (refresh_hp_wm) trefi count level that turns the refresh priority to high (default is 8) 7:0 rw-l 0fh uncore rank idle timer for opportunistic refresh (oref_ri) rank idle period that defines an opportunity for refresh, in dclk cycles processor configuration registers 258 datasheet, volume 2 2.14.8 tc_rftp_c1?refresh ti ming parameters register thie register provides refresh timing parameters. 2.14.9 tc_srftp_c1?self refresh timing parameters register thie register provides self-refresh timing parameters. b/d/f/type: 0/0/0/mchbar mc1 address offset: 4698?469bh reset value: 46b41004h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:25 rw-l 23h uncore 9 * trefi (trefix9) period of minimum between 9*trefi and tras maximum (normally 70 us) in 1024 * dclk cycles (default is 35h) ? need to reduce 100 dclk cycles ? uncertai nty on timing of panic refresh 24:16 rw-l 0b4h uncore refresh execution time (trfc) time of refresh ? from beginning of refresh until next act or refresh is allowed (in dclk cycles, default is 180h) 15:0 rw-l 1004h uncore trefi period in dclk cycles (trefi) defines the average period between refreshes, and the rate that trefi counter is incremented (in dclk cycles, default is 4100h) b/d/f/type: 0/0/0/mchbar mc1 address offset: 46a4?46a7h reset value: 0100b200h access: rw-l size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:28 rw-l 0h uncore (tmod) the time between mrs command and any other command in dclk cycles. actual value is 8 + programmed-value. for example when programming 4 in the field, tm od value is actually 12 dclk cycles. 27:26 ro 0h reserved (rsvd) 25:16 rw-l 100h uncore (tzqoper) this field defines the period re quired for zqcl after sr exit. 15:12 rw-l bh uncore (txs_offset) delay from sr exit to the first ddr command. txs = trfc+10ns. setup of txs_offs et is # of cycles for 10 ns. the range is between 3 and 11 dclk cycles. 11:0 rw-l 200h uncore (txsdll) delay between ddr sr exit and the first command that requires data rd/wr from ddr is in the range of 128 to 1024 dclk cycles, though all jedec ddrs assume 512 dclk cycles. datasheet, volume 2 259 processor configuration registers 2.15 mchbar registers in memory controller ? integrated memory peripheral hub (imph) 2.15.1 crdtctl3?credit control 3 register this register will have the minimum read return tracker credits for each of the peg/dmi/gsa streams. table 2-18. mchbar registers in memory controller ?integrated memory peripheral hub (imph) register address map address offset register symbol register name reset value access 0?740bh rsvd reserved ? ? 740c?740fh crdtctl3 credit control 3 b124f851h rw-l 7410?7413h crdtctl4 credit control 4 00000017h rw-l 7410c?7fffh rsvd reserved ? ? b/d/f/type: 0/0/ 0/mchbar imph address offset: 740c?740fh reset value: b124f851h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:27 rw-l 16h uncore gsa vc1 minimum completion credits (gsavc1) minimum number of credits for gsa vc1 completions 26:24 rw-l 1h uncore gsa vc0 minimum completion credits (gsavc0) minimum number of credits for gsa vc0 completions 23:21 rw-l 1h uncore peg60 vc0 minimum completion credits (peg60vc0) minimum number of credits for peg60 vc0 completions 20:18 rw-l 1h uncore peg12 vc0 minimum completion credits (peg12vc0) minimum number of credits for peg12 vc0 completions 17:15 rw-l 1h uncore peg11 vc0 minimum completion credits (peg11vc0) minimum number of credits for peg11 vc0 completions 14:12 rw-l 7h uncore peg10 vc0 minimum completion credits (peg10vc0) minimum number of credits for peg10 vc0 completions 11:9 rw-l 4h uncore dmi vc1 minimum completion credits (dmivc1) minimum number of credits for dmi vc1 completions 8:6 rw-l 1h uncore dmi vcm minimum completion credits (dmivcm) minimum number of credits for dmi vcm completions 5:3 rw-l 2h uncore dmi vcp minimum completion credits (dmivcp) minimum number of credits for dmi vcp completions 2:0 rw-l 1h uncore dmi vc0 minimum completion credits (dmivc0) minimum number of credits for dmi vc0 completions processor configuration registers 260 datasheet, volume 2 2.15.2 crdtctl4?credit control 4 register this register will have the minimum read return tracker credits for each of the peg/dmi/gsa streams. b/d/f/type: 0/0/0/mchbar imph address offset: 7410?7413h reset value: 00000017h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:6 ro 0h uncore reserved (rsvd) 5:0 rw-l 17h uncore read return tracker shared credits (rdrt_shrd) this field indicates the number of credits that are in the rdrtrn shared pool. bios should configure this field to a value that is equal to 64 minus the sum of all minimum dedicated rdrtn credits. datasheet, volume 2 261 processor configuration registers 2.16 mchbar registers in memory controller ? common 2.16.1 mad_chnl?address deco der channel configuration register this register defines which channel is assigned to be channel a, channel b, and channel c according to the rule: size(a) size (b) size(c) since the processor implements only two cha nnels, channel c is always channel 2, and its size is always 0. table 2-19. mchbar registers in memory co ntroller ? common register address map address offset register symbol register name reset value access 0?4fffh rsvd reserved 0h ro 5000?5003h mad_chnl address decoder channel configuration 00000024h rw-l 5004?5007h mad_dimm_ch0 address decode channel 0 00600000h rw-l 5008?500bh mad_dimm_ch1 address decode channel 1 00600000h rw-l 500c?505fh rsvd reserved ? ? 5060?5063h pm_sref_config self refresh configuration 000100ffh rw-l 5064?50fbh rsvd reserved ? ? b/d/f/type: 0/0/0/mchbar_mcmain address offset: 5000?5003h reset value: 00000024h access: rw-l size: 32 bits bios optimal default 0000000h bit access reset value rst/ pwr description 31:6 ro 0h reserved (rsvd) 5:4 rw-l 10b uncore channel c assignment (ch_c) ch_c ? defines the smallest channel: 00 = channel 0 01 = channel 1 10 = channel 2 3:2 rw-l 01b uncore channel b assignment (ch_b) ch_b ? defines the mid-size channel: 00 = channel 0 01 = channel 1 10 = channel 2 1:0 rw-l 00b uncore channel a assignment (ch_a) ch_a ? defines the largest channel: 00 = channel 0 01 = channel 1 10 = channel 2 processor configuration registers 262 datasheet, volume 2 2.16.2 mad_dimm_ch0?address decode channel 0 register this register defines channel characteristics ? number of dimms, number of ranks, size, ecc, interleave opti ons, and ecc options. b/d/f/type: 0/0/0/mchbar_mcmain address offset: 5004?5007h reset value: 00600000h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:26 ro 0h reserved (rsvd) 25:24 rw-l 00b uncore ecc is active in the channel (ecc) 00 = no ecc active in the channel 01 = ecc is active in io, ecc logic is not active in this case, on write accesses the data driven on ecc byte is copied from dq 7:0 (to be used in training or iosav) 10 = ecc is disabled in io, but ecc logic is enabled (to be used in ecc4ana mode) 11 = ecc active in both i/o and ecc logic 23 ro 0h reserved (rsvd) 22 rw-l 1b uncore enhanced interleave mode (enh_interleave) 0 = off 1 = on 21 rw-l 1b uncore rank interleave (ri) 0 = off 1 = on 20 rw-l 0b uncore dimm b ddr width (dbw) 0 = x8 chips 1 = x16 chips 19 rw-l 0b uncore dimm a ddr width (daw) 0 = x8 chips 1 = x16 chips 18 rw-l 0b uncore dimm b number of ranks (dbnor) 0 = single rank 1 = dual rank 17 rw-l 0b uncore dimm a number of ranks (danor) 0 = single rank 1 = dual rank 16 rw-l 0b uncore dimm a select (das) selects which of the dimms is di mm a ? should be the larger dimm: 0 = dimm 0 1 = dimm 1 15:8 rw-l 00h uncore size of dimm b (dimm_b_size) size of dimm b in 256 mb multiples 7:0 rw-l 00h uncore size of dimm a (dimm_a_size) size of dimm a in 256 mb multiples datasheet, volume 2 263 processor configuration registers 2.16.3 mad_dimm_ch1?address decode channel 1 register this register defines channel characteristics ? number of dimms, number of ranks, size, ecc, interleave options, and ecc options. b/d/f/type: 0/0/0/mchbar_mcmain address offset: 5008?500bh reset value: 00600000h access: rw-l size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:26 ro 0h reserved (rsvd) 25:24 rw-l 00b uncore ecc is active in the channel (ecc) 00 = no ecc active in the channel 01 = ecc is active in io, ecc logic is not active in this case, on write accesses the data driven on ecc byte is copied from dq 7:0 (to be used in training or iosav) 10 = ecc is disabled in io, bu t ecc logic is enabled (to be used in ecc4ana mode) 11 = ecc active in both i/o and ecc logic 23 ro 0h reserved (rsvd) 22 rw-l 1b uncore enhanced interleave mode (enh_interleave) 0 = off 1 = on 21 rw-l 1b uncore rank interleave (ri) 0 = off 1 = on 20 rw-l 0b uncore dimm b ddr width (dbw) 0 = x8 chips 1 = x16 chips 19 rw-l 0b uncore dimm a ddr width (daw) 0 = x8 chips 1 = x16 chips 18 rw-l 0b uncore dimm b number of ranks (dbnor) 0 = single rank 1 = dual rank 17 rw-l 0b uncore dimm a number of ranks (danor) 0 = single rank 1 = dual rank 16 rw-l 0b uncore dimm a select (das) selects which of the dimms is dimm a ? should be the larger dimm. 0 = dimm 0 1 = dimm 1 15:8 rw-l 00h uncore size of dimm b (dimm_b_size) size of dimm b in 256 mb multiples 7:0 rw-l 00h uncore size of dimm a (dimm_a_size) size of dimm a in 256 mb multiples processor configuration registers 264 datasheet, volume 2 2.16.4 pm_sref_config?self re fresh configuration register this is a self refresh mode control register ? defines if and when ddr can go into sr. b/d/f/type: 0/0/0/mchbar_mcmain address offset: 5060?5063h reset value: 000100ffh access: rw-l size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:0 rw-l 00ffh uncore idle timer init value (idle_timer) this value is used when the ?sref_enable? field is set. it defines the number of cycles that there should not be any transaction in order to enter self-refresh. it is programmable 1 to 64k-1. in dclk=800 it determines time of up to 82 us. datasheet, volume 2 265 processor configuration registers 2.17 memory controller mmio registers broadcast group registers table 2-20. memory controller mmio register s broadcast group register address map address offset register symbol register name reset value access 0?4cafh rsvd reserved ? ? 4cb0?4cb3h pm_pdwn_conf ig power-down configuration 00000000h rw-l 4cb4?4cc7h rsvd reserved ? ? 4cc8?4ccbh eccerrlog0 ecc error log 0 00000000h ros-v 4ccc?4ccfh eccerrlog1 ecc error log 1 00000000h ros-v 4cd0?4f83h rsvd reserved ? ? 4f84?4f87h pm_cmd_pwr power management command power 00000000h rw-lv 4f88?4f8bh pm_bw_limit_ config bw limit configuration ffff03ffh rw-l 4f8c?4f8fh rsvd reserved ff1d1519h rw-l processor configuration registers 266 datasheet, volume 2 2.17.1 pm_pdwn_config?power-do wn configuration register this register defines the power-down (cke-off) operation ? power-down mode, idle timer and global / per rank decision. b/d/f/type: 0/0/0/mchbar_mcbcast address offset: 4cb0?4cb3h reset value: 00000000h access: rw-l size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:13 ro 0h reserved (rsvd) 12 rw-l 0b uncore global power-down (glpdn) global power down. when this bit is set, the power-down decision is global for channel. when this register is clear, a separate decision is taken for each rank. 11:8 rw-l 0h uncore power-down mode (pdwn_mode) selects the mode of power-down. all encodings not in table are reserved. note: when selecting dll-off or apd-dll off, dimm mr0 register bit 12 (ppd) must equal 0. note: when selecting apd, ppd or apd-ppd dimm mr0 register bit 12 (ppd) must equal 1. the value 0h (no power-down) is a don't care. 0h = no power-down 1h = apd 2h = ppd 3h = apd+ppd 4h = reserved 5h = reserved 6h = ppd_dlloff 7h = apd+ppd_dlloff 8h?fh = reserved 7:0 rw-l 00h uncore power-down idle timer (pdwn_idle_counter) this field defines the rank idle period in dclk cycles that causes power-down entrance. datasheet, volume 2 267 processor configuration registers 2.17.2 eccerrlog0?ecc error log 0 register 2.17.3 eccerrlog1?ecc error log 1 register b/d/f/type: 0/0/0/mchbar_mcbcast address offset: 4cc8?4ccbh reset value: 00000000h access: ros-v size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:29 ros-v 000b powergood error bank (errbank) this field holds the bank address of the read transaction that had the ecc error. 28:27 ros-v 00b powergood error rank (errrank) this field holds the rank id of the read transaction that had the ecc error. 26:24 ros-v 000b powergood error chunk (errchunk) holds the chunk number of the error stored in the register. 23:16 ros-v 00h powergood error syndrome (errsynd) this field contains the error syndrome. a value of ffh indicates that the error is due to poisoning. 15:2 ro 0h reserved (rsvd) 1 ros-v 0b powergood uncorrectable error status (merrsts) this bit is set when an uncorrect able multiple-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. 0 ros-v 0b powergood correctable error status (cerrsts) this bit is set when a correctable single-bit error occurs on a memory read data transfer. when this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. a multiple bit error that occurs af ter this bit is set will override the address/error syndrome information. this bit is cleared when the corresponding bit in 0.0.0.pci.errsts is cleared. b/d/f/type: 0/0/0/mchbar_mcbcast address offset: 4ccc?4ccfh reset value: 00000000h access: ros-v size: 32 bits bit access reset value rst/ pwr description 31:16 ros-v 0000h powergood error column (errcol) this field holds the dram column address of the read transaction that had the ecc error. 15:0 ros-v 0000h powergood error row (errrow) this field holds the dram row (page) address of the read transaction that had the ecc error. processor configuration registers 268 datasheet, volume 2 2.17.4 pm_cmd_pwr? power management command power register this register defines the power contributi on of each command ? act+pre, cas-read, and cas write. assumption is that the act is always followed by a pre (although not immediately), and ref commands are issued in a fixed rate and there is no need to count them. the register has 3 8-bit fields. 2.17.5 pm_bw_limit_config?bw limit configuration register this register defines the bw throttling at temperature. note: the field ?bw_limit_tf may not be changed in run-time. other fields may be changed in run-time. b/d/f/type: 0/0/0/mchbar_mcbcast address offset: 4f84?4f87h reset value: 00000000h access: rw-lv size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 0h reserved (rsvd) 23:16 rw-lv 00h uncore power contribution of cas write command (pwr_cas_w) 15:8 rw-lv 00h uncore power contribution of cas read command (pwr_cas_r) 7:0 rw-lv 00h uncore power contribution of ras command and pre command (pwr_ras_pre) power contribution of ras command and pre command. the value should be the sum of the two commands, assuming that each ras command for a given page is followed by a pre command to the same page in the near future. b/d/f/type: 0/0/0/mchbar_mcbcast address offset: 4f88?4f8bh reset value: ffff03ffh access: rw-l size: 32 bits bios optimal default 5f7003ffh bit access reset value rst/ pwr description 31:24 rw-l ffh uncore bw limit when rank is hot (bw_limit_hot) number of transactions allowed per rank when status of rank is hot. range: 0?255h 23:16 rw-l ffh uncore bw limit when rank is warm (bw_limit_warm) number of transactions allowed per rank when status of rank is warm. range: 0?255h 15:10 ro 0h reserved (rsvd) 9:0 rw-l 3ffh uncore bw limit time frame (bw_limit_tf) time frame in which the bw limit is enforced, in dclk cycles. range: 1?1023h note: the field ?bw_limit_tf may not be changed in run-time. datasheet, volume 2 269 processor configuration registers 2.18 integrated graphics vtd remapping engine registers table 2-21. integrated graphics vtd remapping engine register addr ess map (sheet 1 of 2) address offset register symbol register name reset value access 0?3h ver_reg version register 00000010h ro 4?7h rsvd reserved 0h ro 8?fh cap_reg capability register 00c0000020 e60262h ro 10?17h ecap_reg extended capability register 0000000000 f0101ah ro, ro-v 18?1bh gcmd_reg global command register 00000000h ro, wo 1c?1fh gsts_reg global status register 00000000h ro-v, ro 20?27h rtaddr_reg root-entry table address register 0000000000 000000h rw 28?2fh ccmd_reg context command register 0800000000 000000h rw, rw-v, ro- v 30?33h rsvd reserved 0h ro 34?37h fsts_reg fault status register 00000000h ro, ros-v, rw1cs 38?3bh fectl_reg fault event control register 80000000h rw, ro-v 3c?3fh fedata_reg fault event data register 00000000h rw 40?43h feaddr_reg fault event address register 00000000h rw 44?47h feuaddr_reg fault event upper address register 00000000h rw 48?57h rsvd reserved 0h ro 58?5fh aflog_reg advanced fault log register 0000000000 000000h ro 60?63h rsvd reserved 0h ro 64?67h pmen_reg protected memory enable register 00000000h rw, ro-v 68?6bh plmbase_reg protected low-memory base register 00000000h rw 6c?6fh plmlimit_reg protected low-memory limit register 00000000h rw 70?77h phmbase_reg protected high-memory base register 0000000000 000000h rw 78?7fh phmlimit_reg protected high-memory limit register 0000000000 000000h rw 80?87h iqh_reg invalidation queue head register 0000000000 000000h ro-v 88?8fh iqt_reg invalidation queue tail register 0000000000 000000h rw-l 90?97h iqa_reg invalidation queue address register 0000000000 000000h rw-l 98?9bh rsvd reserved 0h ro 9c?9fh ics_reg invalidation completion status register 00000000h rw1cs a0?a3h iectl_reg invalidation event control register 80000000h rw-l, ro-v a4?a7h iedata_reg invalidation event data register 00000000h rw-l a8?abh ieaddr_reg invalidation ev ent address register 00000000h rw-l processor configuration registers 270 datasheet, volume 2 2.18.1 ver_reg?version register this register reports the architecture vers ion supported. backward compatibility for the architecture is maintained with new revi sion numbers, allowing software to load remapping hardware drivers written for prior architecture versions. ac?afh ieuaddr_reg invalidation event upper address register 00000000h rw-l b0?b7h rsvd reserved 0h ro b8?bfh irta_reg interrupt remapping table address register 000000000 0000000h rw-l c0?ffh rsvd reserved 0h ro 100?107h iva_reg invalidate address register 000000000 0000000h rw 108?10fh iotlb_reg iotlb invalidate register 020000000 0000000h ro-v, rw, rw-v 110?1ffh rsvd reserved 0h ro 200?207h frcdl_reg fault recording low register 000000000 0000000h ros-v 208?20fh frcdh_reg fault recording high register 0000000000 000000h ro, rw1cs, ros-v 210?fefh rsvd reserved 0h ro ff0?ff3h vtpolicy dma remap engine policy control 00000000h rw-l, ro, ro- kfw, rw-kl table 2-21. integrated graphics vtd remapping engine register address map (sheet 2 of 2) address offset register symbol register name reset value access b/d/f/type: 0/0/0/gfxvtbar address offset: 0?3h reset value: 00000010h access: ro size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:4 ro 0001b uncore major version number (max) indicates supported architecture version. 3:0 ro 0000b uncore minor version number (min) indicates supported architecture minor version. datasheet, volume 2 271 processor configuration registers 2.18.2 cap_reg?capability register this register reports general remapping hardware capabilities. b/d/f/type: 0/0/0/gfxvtbar address offset: 8?fh reset value: 00c0000020e60262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description 63:56 ro 0h reserved (rsvd) 55 ro 1b uncore dma read draining (drd) 0 = hardware does not support draining of dma read requests. 1 = hardware supports draining of dma read requests. 54 ro 1b uncore dma write draining (dwd) 0 = hardware does not support draining of dma write requests. 1 = hardware supports draining of dma write requests. 53:48 ro 000000b uncore maximum address mask value (mamv) the value in this field indicate s the maximum supported value for the address mask (am) field in the invalidation address register (iva_reg) and iotlb invalidation descriptor (iotlb_inv_dsc). this field is valid only when the psi field in capability register is reported as set. 47:40 ro 00000000 b uncore number of fault-recording registers (nfr) number of fault recording registers is computed as n+1, where n is the value report ed in this field. implementations must support at least one fault recording register (nfr = 0) for each remapping hardware unit in the platform. the maximum number of fault re cording registers per remapping hardware unit is 256. 39 ro 0b uncore page selective invalidation (psi) 0 = hardware supports only domain and global invalidates for iotlb 1 = hardware supports page selective, domain and global invalidates for iotlb. hardware implementations reporting this field as set are recommended to support a maximum address mask value (mamv) value of at least 9. 38:38 ro 0h reserved (rsvd) 37:34 ro 0000b uncore super-page support (sps) this field indicates the super page sizes supported by hardware. a value of 1 in any of these bits indicates the corresponding super-page size is supported. the super-page sizes corresponding to various bit positions within this field are: 0 = 21-bit offset to page frame (2 mb) 1 = 30-bit offset to page frame (1 gb) 2 = 39-bit offset to page frame (512 gb) 3 = 48-bit offset to page frame (1 tb) hardware implementations supporting a specific super-page size must support all smaller super-pa ge sizes; that is, only valid values for this field are 0001b, 0011b, 0111b, 1111b. processor configuration registers 272 datasheet, volume 2 33:24 ro 020h uncore fault-recording register offset (fro) this field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the fi rst fault recording register is calculated as x+(16*y). 23 ro 1b uncore isochrony (isoch) 0 = remapping hardware unit has no critical isochronous requesters in its scope. 1 = remapping hardware unit has one or more critical isochronous requesters in its scope. to ensure isochronous performance, software must ensure invalidation operations do not impact active dma streams from such requesters. this implies, when dma is ac tive, software performs page- selective invalidations (and not coarser invalidations). 22 ro 1b uncore zero length read (zlr ) 0 = remapping hardware unit blocks (and treats as fault) zero length dma read requests to write-only pages. 1 = remapping hardware unit supports zero length dma read requests to write-only pages. dma remapping hardware implementations are recommended to report zlr field as set. 21:16 ro 100110b uncore maximum guest address width (mgaw) this field indicates the maxi mum dma virtual addressability supported by remapping hardware. the maximum guest address width (mgaw) is computed as (n+1), where n is the value reported in this field. for example, a hardware implementation supporting 48-bit mgaw reports a value of 47h (101111b) in this field. if the value in this field is x, untranslated and translated dma requests to addresses above 2^(x+1)?1 are always blocked by hardware. translations requests to address above 2^(x+1)?1 from allowed devices return a null translation completion data entry with r=w=0. guest addressability for a given dma request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structure. (adjusted guest address widths supported by hardware are reported through the sagaw field). implementations are recommended to support mgaw at least equal to the physical addressab ility (host address width) of the platform. 15:13 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/gfxvtbar address offset: 8?fh reset value: 00c0000020e60262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description datasheet, volume 2 273 processor configuration registers 12:8 ro 00010b uncore supported adjusted guest address widths (sagaw) this 5-bit field indicates the su pported adjusted guest address widths (which in turn represents the levels of page-table walks for the 4 kb base page size) supported by the hardware implementation. a value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. the adjusted guest address widths corresponding to various bit positions within this field are: 0 = 30-bit agaw (2-level page table) 1 = 39-bit agaw (3-level page table) 2 = 48-bit agaw (4-level page table) 3 = 57-bit agaw (5-level page table) 4 = 64-bit agaw (6-level page table) software must ensure that th e adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field. 7ro 0buncore caching mode (cm) 0 = not-present and erroneous entries are not cached in any of the remapping caches. invalidat ions are not required for modifications to individual not present or invalid entries. however, any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective. 1 = not-present and erroneous mappings may be cached in the remapping caches. any software updates to the remapping structures (including updates to "not-present" or erroneous entries) require explicit invalidation. hardware implementations of this architecture must support a value of 0 in this field. 6ro 1buncore protected high-memory region (phmr) 0 = protected high-memory region is not supported. 1 = protected high-memory region is supported. 5ro 1buncore protected low-memory region (plmr) 0 = protected low-memory region is not supported. 1 = protected low-memory region is supported. b/d/f/type: 0/0/0/gfxvtbar address offset: 8?fh reset value: 00c0000020e60262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description processor configuration registers 274 datasheet, volume 2 4ro 0buncore required write-buffer flushing (rwbf ) 0 = no write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware. 1 = software must explicitly flus h the write buffers to ensure updates made to memory-resid ent remapping structures are visible to hardware. 3ro 0buncore advanced fault logging (afl) 0 = advanced fault logging is no t supported. only primary fault logging is supported. 1 = advanced fault logging is supported. 2:0 ro 010b uncore number of domains supported (nd) 000 = hardware supports 4-bit doma in-ids with support for up to 16 domains. 001 = hardware supports 6-bit doma in-ids with support for up to 64 domains. 010 = hardware supports 8-bit doma in-ids with support for up to 256 domains. 011 = hardware supports 10-bit domain-ids with support for up to 1024 domains. 100 = hardware supports 12-bit domain-ids with support for up to 4k domains. 100 = hardware supports 14-bit domain-ids with support for up to 16k domains. 110 = hardware supports 16-bit domain-ids with support for up to 64k domains. 111 = reserved. b/d/f/type: 0/0/0/gfxvtbar address offset: 8?fh reset value: 00c0000020e60262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description datasheet, volume 2 275 processor configuration registers 2.18.3 ecap_reg?extended capability register this register reports remapping hardware extended capabilities. b/d/f/type: 0/0/0/gfxvtbar address offset: 10?17h reset value: 0000000000f0101ah access: ro, ro-v size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description 63:24 ro 0h reserved (rsvd) 23:20 ro 1111b uncore maximum handle mask value (mhmv) the value in this field indicate s the maximum supported value for the handle mask (hm) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc). this field is valid only when th e ir field in extended capability register is reported as set. 19:18 ro 0h reserved (rsvd) 17:8 ro 010h uncore iotlb register offset (iro) this field specifies the offset to the iotlb registers relative to the register base address of this remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the fi rst iotlb invalidation register is calculated as x+(16*y). 7ro 0buncore snoop control (sc) 0 = hardware does not support 1-setting of the snp field in the page-table entries. 1 = hardware supports the 1-setting of the snp field in the page-table entries. 6ro 0buncore pass through (pt) 0 = hardware does not support pass-through translation type in context entries. 1 = hardware supports pass-through translation type in context entries. 5ro 0buncore caching hints (ch) 0 = hardware does not support iotlb caching hints (alh and eh fields in context-entries are treated as reserved( 1 = hardware supports ioltb caching hints through the alh and eh fields in context-entries. 4ro 0h reserved (rsvd) 3ro-v 1b uncore interrupt remapping support (ir) 0 = hardware does not support interrupt remapping. 1 = hardware supports interrupt remapping. implementations reporting this field as set must also support queued invalidation (qi) 2ro 0buncore device iotlb support (di) 0 = hardware does not support device-iotlbs. 1 = hardware supports device-iotlbs. implementations reporting this field as set must also support queued invalidation (qi) 1ro-v 1b uncore queued invalidation support (qi) 0 = hardware does not support queued invalidations. 1 = hardware supports queued invalidations. processor configuration registers 276 datasheet, volume 2 2.18.4 gcmd_reg?global command register this register controls remapping hardware. if multiple control fields in this register need to be modified, software must serialize the modifications through multiple writes to this register. 0ro 0buncore coherency (c) this field indicates if hardware access to the root, context, page- table and interrupt-remap structures are coherent (snooped) or not. 0 = hardware accesses to remapping structures are non- coherent. 1 = hardware accesses to remapping structures are coherent. hardware access to advanced faul t log and invalidation queue are always coherent. b/d/f/type: 0/0/0/gfxvtbar address offset: 10?17h reset value: 0000000000f0101ah access: ro, ro-v size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/gfxvtbar address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31 wo 0b uncore translation enable (te) software writes to this field to request hardware to enable/disable dma-remapping: 0 = disable dma remapping 1 = enable dma remapping hardware reports the status of the translation enable operation through the tes field in the global status register. there may be active dma requests in the platform when software updates this field. hardware mu st enable or disable remapping logic only at deterministic transa ction boundaries, so that any in- flight transaction is either subject to remapping or not at all. hardware implementations supporting dma draining must drain any in-flight dma read/write requ ests queued within the root- complex before comple ting the translation enable command and reflecting the status of the command through the tes field in the global status register. the value returned on a read of this field is undefined. datasheet, volume 2 277 processor configuration registers 30 wo 0b uncore set root table pointer (srtp) software sets this field to set/update the root-entry table pointer used by hardware. the root-entry table pointer is specified through the root-entry table address (rta_reg) register. hardware reports the status of the "set root table pointer" operation through the rtps field in the global status register. the "set root table pointer" operation must be performed before enabling or re-enabling (after di sabling) dma re mapping through the te field. after a "set root table pointer" operation, software must globally invalidate the context cache an d then globally invalidate of iotlb. this is required to en sure hardware uses only the remapping structures referenced by the new root table pointer, and not stale cached entries. wh ile dma remapping hardware is active, software may update the root table pointer through this field. however, to ensure va lid in-flight dma requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root-table pointer. clearing this bit has no effect. the value returned on read of this field is undefined. 29 ro 0b uncore set fault log (sfl) this field is valid only for im plementations supporting advanced fault logging. software sets this field to request hardware to set/update the fault-log pointer used by hard ware. the fault-log pointer is specified through advanced fault log register. hardware reports the status of the 'set fault log' operation through the fls field in the global status register. the fault log pointer must be se t before enabling advanced fault logging (through eafl field). once advanced fault logging is enabled, the fault log pointer ma y be updated through this field while dma remapping is active. clearing this bit has no effect. the value returned on read of this field is undefined. 28 ro 0b uncore enable advanced fa ult logging (eafl) this field is valid only for im plementations supporting advanced fault logging. software writes to this field to request hardware to enable or disable advanced fault logging: 0 = disable advanced fault logging. in this case, translation faults are reported through the fault recording registers. 1 = enable use of memory-resident fault log. when enabled, translation faults are recorded in the memory-resident log. the fault log pointer must be set in hardware (through the sfl field) before enabling adva nced fault logg ing. hardware reports the status of the advanced fault logging enable operation through the afls field in the global status register. the value returned on read of this field is undefined. b/d/f/type: 0/0/0/gfxvtbar address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description processor configuration registers 278 datasheet, volume 2 27 ro 0b uncore write buffer flush (wbf) this bit is valid only for impl ementations requiring write buffer flushing. software sets this field to request that hardware flush the root- complex internal writ e buffers. this is done to ensure any updates to the memory-resident remapping structures are not held in any internal write posting buffers. hardware reports the status of the write buffer flushing operation through the wbfs field in the global status register. clearing this bit has no effect. the value returned on a read of this field is undefined. 26 wo 0b uncore queued invalidation enable (qie) this field is valid only for impl ementations supporting queued invalidations. software writes to this field to enable or disable queued invalidations. 0 = disable queued invalidations. 1 = enable use of queued invalidations. hardware reports the status of queued invalidation enable operation through qies field in the global status register. the value returned on a read of this field is undefined. 25 wo 0b uncore interrupt remapping enable (ire) this field is valid only for impl ementations supporting interrupt remapping. 0 = disable interrup t-remapping hardware 1 = enable interrupt-remapping hardware hardware reports the status of the interrupt remapping enable operation through the ires field in the global status register. there may be active interrupt requests in the platform when software updates this field. ha rdware must enable or disable interrupt-remapping logic only at deterministic transaction boundaries, so that an y in-flight interrupts are either subject to remapping or not at all. hardware implementations must drain any in-flight interrupts requests queued in the root-complex before completing the interrupt-remapping enable command and reflecting the status of the command through the ires field in the global status register. the value returned on a read of this field is undefined. b/d/f/type: 0/0/0/gfxvtbar address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description datasheet, volume 2 279 processor configuration registers 24 wo 0b uncore set interrupt remap table pointer (sirtp) this field is valid only for im plementations supporting interrupt- remapping. software sets this field to se t/update the interrupt remapping table pointer used by hardware. the interrupt remapping table pointer is specified through the interrupt remapping table address (irta_reg) register. hardware reports the status of the 'set interrupt remap table pointer? operation through the irtps field in the global status register. the 'set interrupt remap table pointer' operation must be performed before enabling or re-enabling (after disabling) interrupt-remapping hardware through the ire field. after a 'set interrupt remap table pointer' operation, software must globally invalidate the in terrupt entry cache. this is required to ensure hardware uses only the interrupt-remapping entries referenced by the new in terrupt remap table pointer, and not any stale cached entries. while interrupt remapping is ac tive, software may update the interrupt remapping table pointer through this field. however, to ensure valid in-flight interrupt requests are deterministically remapped, software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer. clearing this bit has no effect. the value returned on a read of this field is undefined. 23:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/gfxvtbar address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description processor configuration registers 280 datasheet, volume 2 2.18.5 gsts_reg?global status register this register reports general remapping hardware status. b/d/f/type: 0/0/0/gfxvtbar address offset: 1c?1fh reset value: 00000000h access: ro-v, ro size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31 ro-v 0b uncore translation enable status (tes) this field indicates the status of dma-remapping hardware. 0 = dma-remapping hardware is not enabled 1 = dma-remapping hardware is enabled 30 ro-v 0b uncore root table pointer status (rtps) this field indicates the status of the root- table pointer in hardware. this field is: ? cleared by hardware when software sets the srtp field in the global command register. ? set by hardware when hardware completes the 'set root table pointer' operation using the value provided in the root- entry table address register. 29 ro 0b uncore fault log status (fls) this field is: ? cleared by hardware when software sets the sfl field in the global command register. ? set by hardware when hardware completes the 'set fault log pointer' operation using the value provided in the advanced fault log register. 28 ro 0b uncore advanced fault logging status (afls) this field is valid only for impl ementations supporting advanced fault logging. it indicates the advanced fault logging status: 0 = advanced fault logging is not enabled. 1 = advanced fault logging is enabled. 27 ro 0b uncore write buffer flush status (wbfs) this field is valid only for impl ementations requiring write buffer flushing. this field indicates the status of the write buffer flush command. it is: ? set by hardware when software sets the wbf field in the global command register. ? cleared by hardware when hardware completes the write buffer flushing operation. 26 ro-v 0b uncore queued invalidation enable status (qies) this field indicates queued invalidation enable status. 0 = queued invalidation is not enabled 1 = queued invalidation is enabled 25 ro-v 0b uncore interrupt remapping enable status (ires) this field indicates the status of interrupt-remapping hardware. 0 = interrupt-remapping hardware is not enabled 1 = interrupt-remapping hardware is enabled 24 ro-v 0b uncore interrupt remapping table pointer status (irtps) this field indicates the status of the interrupt remapping table pointer in hardware. this field is: ? cleared by hardware when software sets the sirtp field in the global command register. ? set by hardware when hardware completes the set interrupt remap table pointer operation us ing the value provided in the interrupt remapping table address register. 23:0 ro 0h reserved (rsvd) datasheet, volume 2 281 processor configuration registers 2.18.6 rtaddr_reg?root-entry table address register this register providing the base address of root-entry table. b/d/f/type: 0/0/0/gfxvtbar address offset: 20?27h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 0000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore root table address (rta) this field points to base of page aligned, 4 kb-sized root-entry table in system memory. hardware ignores and not implements bits 63:haw, where haw is the host address width. software specifies the base address of the root-entry table through this register, and programs it in hardware through the srtp field in the global command register. reads of this register returns value that was last programmed to it. 11:0 ro 0h reserved (rsvd) processor configuration registers 282 datasheet, volume 2 2.18.7 ccmd_reg?contex t command register this register manages context cache. the act of writing the uppermost byte of the ccmd_reg with the icc field set causes the hardware to perform the context-cache invalidation. b/d/f/type: 0/0/0/gfxvtbar address offset: 28?2fh reset value: 0800000000000000h access: rw, rw-v, ro-v size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63 rw-v 0h uncore invalidate context-cache (icc) software requests invalidation of context-cache by setting this field. software must also set the requested invalidation granularity by programming the cirg field. software must read back and check the icc field is cl ear to confirm the invalidation is complete. software must not update this register when this field is set. hardware clears the icc field to indicate the invalidation request is complete. hardware also indica tes the granularity at which the invalidation operation was performed through the caig field. software must submit a cont ext-cache invalidation request through this field only when there are no invalidation requests pending at this rema pping hardware unit. since information from the context-cache may be used by hardware to tag iotlb entries, software must perform domain- selective (or global) invalidation of iotlb after the context cache invalidation has completed. hardware implementations reporting write-buffer flushing requirement (rwbf=1 in capabili ty register) must implicitly perform a write buffer flush before invalidating the context cache. 62:61 rw 0h uncore context invalidation request granularity (cirg) software provides the requested invalidation granularity through this field when setting the icc field: 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalidation request. the target domain-id must be specified in the did field. 11 = device-selective invalidation request. the target source- id(s) must be specified through the sid and fm fields, and the domain-id (that was programmed in the context-entry for these device(s)) must be provided in the did field. hardware implementations may pr ocess an invalidation request by performing invalidation at a coarser granularity than requested. hardware indicates completion of the invalidation request by clearing the icc field. at this time, hardware also indicates the granularity at which the actual invalidation was performed through the caig field. datasheet, volume 2 283 processor configuration registers 60:59 ro-v 1h uncore context actual invalidation granularity (caig) hardware reports the granularity at which an invalidation request was processed through the caig field at the time of reporting invalidation completion (by clearing the icc field). the following are the encodings for this field: 00 = reserved. 01 = global invalidation performed. this could be in response to a global, domain-selective or device-selective invalidation request. 10 = domain-selective invalidati on performed using the domain- id specified by software in the did field. this could be in response to a domain-selective or device-selective invalidation request. 11 = device-selective invalidatio n performed using the source-id and domain-id specified by so ftware in the sid and fm fields. this can only be in response to a device-selective invalidation request. 58:34 ro 0h reserved (rsvd) 33:32 rw 0h uncore function mask (fm) software may use the function mask to perform device-selective invalidations on behalf of devices supporting pci express phantom functions. this field specifies which bits of the function number portion (least significant three bits) of the sid field to mask when performing device-selective invalidations. the following encodings are defined for this field: 00 = no bits in the sid field masked. 01 = mask most significant bit of function number in the sid field. 10 = mask two most significant bit of function number in the sid field. 11 mask all three bits of function number in the sid field. the context-entries corresponding to all the source-ids specified through the fm and sid fields must have to the domain-id specified in the did field. 31:16 rw 0000h uncore source id (sid) indicates the source-id of the device whose corresponding context-entry needs to be selectively invalidated. this field along with the fm field must be programmed by software for device- selective invalidation requests. 15:8 ro 0h reserved (rsvd) 7:0 rw 00h uncore domain-id (did) this field indicates the id of the domain whose context-entries need to be selectively inva lidated. this field must be programmed by software for both domain-selective and device- selective invalidation requests. the capability register reports th e domain-id width supported by hardware. software must ensure that the value written to this field is within this limit. hard ware may ignore and not implement bits15:n, where n is the supported domain-id width reported in the capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: 28?2fh reset value: 0800000000000000h access: rw, rw-v, ro-v size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description processor configuration registers 284 datasheet, volume 2 2.18.8 fsts_reg?fault status register this register indicates the various error status. b/d/f/type: 0/0/0/gfxvtbar address offset: 34?37h reset value: 00000000h access: ro, ros-v, rw1cs size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:8 ros-v 00h powergood fault record index (fri) this field is valid only when the ppf field is set. the fri field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the ppf field was set by hardware. the value read from this field is undefined when the ppf field is clear. 7ro 0h reserved (rsvd) 6 ro 0b uncore invalidation time-out error (ite) hardware detected a device-i otlb invalidation completion time-out. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not supporting device device- iotlbs implement this bit as rsvdz. 5 ro 0b uncore invalidation completion error (ice) hardware received an unexpected or invalid device-iotlb invalidation completion. this coul d be due to either an invalid itag or invalid source-id in an invalidation completion response. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as rsvdz. 4 rw1cs 0b powergood invalidation queue error (iqe) hardware detected an error associated with the invalidation queue. this could be due to either a hardware error while fetching a descriptor from the invalidation queue, or hardware detecting an erroneous or invali d descriptor in the invalidation queue. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not supporting queued invalidations implement this bit as rsvdz. 3 ro 0b uncore advanced pending fault (apf) when this field is clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supporti ng advanced fault logging implement this bit as rsvdz. datasheet, volume 2 285 processor configuration registers 2ro 0b uncore advanced fault overflow (afo) hardware sets this field to indicate advanced fault log overflow condition. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supporting advanced fault logging implement this bit as rsvdz. 1ros-v 0b powergood primary pending fault (ppf) this field indicates if there are one or more pending faults logged in the fault recording registers. hardware computes this field as the logical or of fault (f) fields across all the fault recording registers of this remapping hardware unit. 0 = no pending faults in any of the fault recording registers 1 = one or more fault recording registers has pending faults. the fri field is updated by hardware whenever the ppf field is set by hardware. also, depending on the programming of fault event control register, a fault event is generated when hardware sets this field. 0 rw1cs 0b powergood primary fault overflow (pfo) hardware sets this field to indi cate overflow of fault recording registers. software writing 1 clears this field. when this field is set, hardware does not record any new faults until software clears this field. b/d/f/type: 0/0/0/gfxvtbar address offset: 34?37h reset value: 00000000h access: ro, ros-v, rw1cs size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description processor configuration registers 286 datasheet, volume 2 2.18.9 fectl_reg?fault event control register this register specifies the fault event interrupt message control bits. b/d/f/type: 0/0/0/gfxvtbar address offset: 38?3bh reset value: 80000000h access: rw, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw 1b uncore interrupt mask (im ) 0 = no masking of interrupt. wh en an interrupt condition is detected, hardware issues an interrupt message (using the fault event data and fault event address register values). 1 = this is the value on reset. software may mask interrupt message generation by setting this field. hardware is prohibited from sending the interrupt message when this field is set. 30 ro-v 0h uncore interrupt pending (ip) hardware sets the ip field whenever it detects an interrupt condition, which is defined as: when primary fault logging is active, an interrupt condition occurs when hardware records a fault through one of the fault recording registers and sets the ppf field in fault status register. when advanced fault logging is active, an interrupt condition occurs when hardware records a fault in the first fault record (at index 0) of the current fault log and sets the apf field in the fault status register. hardware detected error associated with the invalidation queue, setting the iqe field in the fault status register. hardware detected invalid device -iotlb invalidation completion, setting the ice field in the fault status register. hardware detected device-iotlb invalidation completion time- out, setting the ite field in the fault status register. if any of the status fields in the fault status register was already set at the time of setting any of these fields, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. the interrupt message could be held pending due to interrupt mask (im field) being set or other transient hardware conditions. the ip field is cleared by hardware as soon as the interrupt message pending condition is se rviced. this could be due to either: ? hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending, or due to software clearing the im field. ? software servicing all the pendin g interrupt status fields in the fault status register as follows: ? when primary fault logging is active, software clearing the fault (f) field in all the fault recording registers with faults, causing the ppf field in fault status register to be evaluated as clear. ? software clearing other status fields in the fault status register by writing back the value read from the respective fields. 29:0 ro 0h reserved (rsvd) datasheet, volume 2 287 processor configuration registers 2.18.10 fedata_reg?faul t event data register this register specifies the interrupt message data. 2.18.11 feaddr_reg?fault event address register this register specifies the interrupt message address. 2.18.12 feuaddr_reg?fault event upper address register this register specifies the interrupt message upper address. b/d/f/type: 0/0/0/gfxvtbar address offset: 3c?3fh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:16 rw 0000h uncore extended interrupt message data (eimd): this field is valid only for implementations supporting 32-bit interrupt data fields. hardware implementations supporti ng only 16-bit interrupt data may treat this field as rsvdz. 15:0 rw 0000h uncore interrupt message data (imd): data value in the interrupt request. b/d/f/type: 0/0/0/gfxvtbar address offset: 40?43h reset value: 00000000h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:2 rw 00000000h uncore message address (ma) when fault events are enabled, the contents of this register specify the dword-alig ned address (bits 31:2) for the interrupt request. 1:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/gfxvtbar address offset: 44?47h reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore message upper address (mua) hardware implementations suppor ting extended interrupt mode are required to implement this register. hardware implementations not su pporting extended interrupt mode may treat this field as rsvdz. processor configuration registers 288 datasheet, volume 2 2.18.13 aflog_reg?advanc ed fault log register this register specifies the base address of the memory-resident fault-log region. this register is treated as rsvdz for implementa tions not supporting advanced translation fault logging (afl field reported as 0 in the capability register). b/d/f/type: 0/0/0/gfxvtbar address offset: 58?5fh reset value: 0000000000000000h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description 63:12 ro 00000000 00000h uncore fault log address (fla) this field specifies the base of 4 kb aligned fault-log region in system memory. hardware ignore s and does not implement bits 63:haw, where haw is the host address width. software specifies the base address and size of the fault log region through this register, and programs it in hardware through the sfl field in the global command register. when implemented, reads of this field return the value that was last programmed to it. 11:9 ro 0h uncore fault log size (fls) this field specifies the size of th e fault log region pointed by the fla field. the size of the fault log region is 2^x * 4kb, where x is the value programmed in this register. when implemented, reads of this field return the value that was last programmed to it. 8:0 ro 0h reserved (rsvd) datasheet, volume 2 289 processor configuration registers 2.18.14 pmen_reg?protected memory enable register this register enables the dma-protected me mory regions setup through the plmbase, plmlimt, phmbase, phmlimit registers. this register is always treated as ro for implementations not supporting protected memory regions (plmr and phmr fields reported as clear in the capability register). protected memory regions may be used by software to securely initialize remapping structures in memory. to avoid impact to legacy bios usage of memory, software is recommended to not overlap protected memo ry regions with any reserved memory regions of the platform reported through the reserved memory region reporting (rmrr) structures. b/d/f/type: 0/0/0/gfxvtbar address offset: 64?67h reset value: 00000000h access: rw, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw 0h uncore enable protected memory (epm) this field controls dma accesses to the protected low-memory and protected high-memory regions. 0 = protected memory regions are disabled. 1 = protected memory regions are enabled. dma requests accessing protected memory regions are handled as follows: ? when dma remapping is not enabled, all dma requests accessing protected memory regions are blocked. ? when dma remapping is enabled: ? dma requests processed as pass-through (translation type value of 10b in context-entry) and accessing the protected memory regions are blocked. ? dma requests with translated address (at=10b) and accessing the protected memory regions are blocked. ? dma requests that are subj ect to address remapping, and accessing the protected memory regions may or may not be blocked by hardware. for such requests, software must not depend on hardware protection of the protected memory regions, and instead program the dma-remapping page-tables to not allow dma to protected memory regions. remapping hardware access to the remapping structures are not subject to protected memory region checks. dma requests blocked due to protected memory region violation are not recorded or reported as remapping faults. hardware reports the status of the protected memory enable/disable operation through the prs field in this register. hardware implementations suppor ting dma draining must drain any in-flight translated dma requests queued within the root- complex before indicating the protected memory region as enabled through the prs field. 30:1 ro 0h reserved (rsvd) 0ro-v 0h uncore protected region status (prs) this field indicates the status of protected memory regions: 0 = protected memory region(s) disabled. 1 = protected memory region(s) enabled. processor configuration registers 290 datasheet, volume 2 2.18.15 plmbase_reg?protected low-memory base register this register sets up the base address of dma-protected low-memory region below 4 gb. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as clear in the capability register). the alignment of the protected low memory region base depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding the most significant zero bit position with 0 in the value read back from the register. bits n:0 of this register are decoded by hardware as all 0s. software must setup the protected low memory region below 4 gb. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/gfxvtbar address offset: 68?6bh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw 000h uncore protected low-memory base (plmb) this field specifies the base of protected low-memory region in system memory. 19:0 ro 0h reserved (rsvd) datasheet, volume 2 291 processor configuration registers 2.18.16 plmlimit_reg?protected low-memory limit register this register sets up the limit address of dma-protected low-memory region below 4 gb. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as clear in the capability register). the alignment of the protected low memory region limit depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding most significant zero bi t position with 0 in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected low-memory base and limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits 31)n+1) specifies a protected low-memory region of size 2^(n+1) bytes. ? programming the protected low-memory limit register with a value less than the protected low-memory base register disables the protected low-memory region. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/gfxvtbar address offset: 6c?6fh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw 000h uncore protected low-memory limit (plml) this register specifies the last host physical address of the dma- protected low-memory region in system memory. 19:0 ro 0h reserved (rsvd) processor configuration registers 292 datasheet, volume 2 2.18.17 phmbase_reg?protected high-memory base register this register sets up the base address of dma-protected high-memory region. this register must be set up before enablin g protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as clear in the capability register). the alignment of the protected high memory region base depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of this register are decoded by hardware as all 0s. software may setup the protected high memory region either above or below 4 gb. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/gfxvtbar address offset: 70?77h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw 00000h uncore protected high-memory base (phmb) this register specifies the base of protected (high) memory region in system memory. hardware ignores, and does not implement, bits 63:haw, where haw is the host address width. 19:0 ro 0h reserved (rsvd) datasheet, volume 2 293 processor configuration registers 2.18.18 phmlimit_reg?protected high-memory limit register this register sets up the limit address of dma-protected high-memory region. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protec ted memory regions are enabled. this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as clear in the capability register). the alignment of the protected high memory region limit depends on the number of reserved bits (n:0) of this register. softwa re may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected high-memory base & limit registers functions as follows. ? programming the protected low-memory base and limit registers with the same value in bits haw:(n+1) specifies a protected low-memory region of size 2^(n+1) bytes. ? programming the protected high-memory limit register with a value less than the protected high-memory base register disables the protected high-memory region. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/gfxvtbar address offset: 78?7fh reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw 00000h uncore protected high-memory limit (phml) this register specifies the last host physical address of the dma- protected high-memory region in system memory. hardware ignores and does not implement bits 63:haw, where haw is the host address width. 19:0 ro 0h reserved (rsvd) processor configuration registers 294 datasheet, volume 2 2.18.19 iqh_reg?invalidati on queue head register this register indicates the invalidation queue head. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. 2.18.20 iqt_reg?invalidati on queue tail register this register indicates the invalidation tail head. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: 80?87h reset value: 0000000000000000h access: ro-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63:19 ro 0h reserved (rsvd) 18:4 ro-v 0000h uncore queue head (qh): specifies the offset (128-bit aligne d) to the invalidation queue for the command that will be fetched next by hardware. hardware resets this field to 0 whenever the queued invalidation is disabled (qies field clear in the global status register). 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/gfxvtbar address offset: 88?8fh reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63:19 ro 0h reserved (rsvd) 18:4 rw-l 0000h uncore queue tail (qt) this field specifies the offset ( 128-bit aligned) to the invalidation queue for the command that will be written next by software. 3:0 ro 0h reserved (rsvd) datasheet, volume 2 295 processor configuration registers 2.18.21 iqa_reg?invalidation queue address register this register configures the base address and size of the invalidation queue. this register is treated as rsvdz by implementa tions reporting queued invalidation (qi) as not supported in the exte nded capability register. 2.18.22 ics_reg?invalidation completion status register this register reports completion status of invalidation wait descriptor with interrupt flag (if) set. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: 90?97h reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw-l 0000000h uncore invalidation queue base address (iqa) this field points to the base of 4 kb aligned invalidation request queue. hardware ignores and does not implement bits 63:haw, where haw is the host address width. reads of this field return the value that was last programmed to it. 11:3 ro 0h reserved (rsvd) 2:0 rw-l 0h uncore queue size (qs) this field specifies the size of the invalidation request queue. a value of x in this field indicate s an invalidation request queue of (2^x) 4 kb pages. the number of entries in the invalidation queue is 2^(x + 8). b/d/f/type: 0/0/0/gfxvtbar address offset: 9c?9fh reset value: 00000000h access: rw1cs size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:1 ro 0h reserved (rsvd) 0 rw1cs 0b powergood invalidation wait descriptor complete (iwc) this bit indicates completion of invalidation wait descriptor with interrupt flag (if) field se t. hardware implementations not supporting queued invalidations implement this field as rsvdz. processor configuration registers 296 datasheet, volume 2 2.18.23 iectl_reg?invalidati on event control register this register specifies the invalid ation event interrupt control bits. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: a0?a3h reset value: 80000000h access: rw-l, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw-l 1b uncore interrupt mask (im) 0 = no masking of interrupt. when an invalidation event condition is detected, hardware issues an interrupt message (using the invalidation event data & invalidation event address register values). 1 = this is the value on reset. software may mask interrupt message generation by setting this field. hardware is prohibited from sending the interrupt message when this field is set. 30 ro-v 0b uncore interrupt pending (ip) hardware sets the ip field whenever it detects an interrupt condition. interrupt condition is defined as: ? an invalidation wait descriptor with interrupt flag (if) field set completed, setting the iwc field in the invalidation completion status register. ? if the iwc field in the invalidation completion status register was already set at the time of setting this field, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. the interrupt message could be held pending due to interrupt mask (im field) being set, or due to other transient hardware conditions. the ip field is cleared by hardware as soon as the interrupt messag e pending condition is serviced. this could be due to either: ? hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the im field. ? software servicing the iwc field in the invalidation completion status register. 29:0 ro 0h reserved (rsvd) datasheet, volume 2 297 processor configuration registers 2.18.24 iedata_reg?invalidat ion event data register this register specifies the invalidation event interrupt message data. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. 2.18.25 ieaddr_reg?invalidation event address register this register specifies the invalidat ion event interrupt message address. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: a4?a7h reset value: 00000000h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:16 rw-l 0000h uncore extended interrupt message data (eimd) this field is valid only for implementations supporting 32-bit interrupt data fields. hardware implementations supporti ng only 16-bit interrupt data treat this field as rsvd. 15:0 rw-l 0000h uncore interrupt message data (imd) data value in the interrupt request. b/d/f/type: 0/0/0/gfxvtbar address offset: a8?abh reset value: 00000000h access: rw-l size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:2 rw-l 00000000 h uncore message address (ma) when fault events are enabled, the contents of this register specify the dword-alig ned address (bits 31:2) for the interrupt request. 1:0 ro 0h reserved (rsvd) processor configuration registers 298 datasheet, volume 2 2.18.26 ieuaddr_reg?i nvalidation event upper address register this register specifies the invalidatio n event interrupt message upper address. 2.18.27 irta_reg?interrupt rema pping table a ddress register this register provides the base address of interrupt remapping table. this register is treated as rsvdz by implem entations reporting interrupt remapping (ir) as not supported in the extended capability register. b/d/f/type: 0/0/0/gfxvtbar address offset: ac?afh reset value: 00000000h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:0 rw-l 00000000h uncore message upper address (mua) hardware implementations supporting queued invalidations and extended interrupt mode are requir ed to implement this register. hardware implementations not su pporting queued invalidations or extended interrupt mode ma y treat this field as rsvdz. b/d/f/type: 0/0/0/gfxvtbar address offset: b8?bfh reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 00000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw-l 0000000h uncore interrupt remapping table address (irta) this field points to the base of 4 kb aligned interrupt remapping table. hardware ignores and does not implement bits 63:haw, where haw is the host address width. reads of this field returns value that was last programmed to it. 11:4 ro 0h reserved (rsvd) 3:0 rw-l 0h uncore size (s) this field specifies the size of the interrupt remapping table. the number of entries in the interrupt remapping table is 2^(x+1), where x is the value programmed in this field. datasheet, volume 2 299 processor configuration registers 2.18.28 iva_reg?invalidate address register this register provides the dma address whose corresponding iotlb entry needs to be invalidated through the corresponding iotlb invalidate register. this register is a write-only register. b/d/f/type: 0/0/0/gfxvtbar address offset: 100?107h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 00000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore address (addr) software provides the dma addr ess that needs to be page- selectively invalidated. to make a page-selective invalidation request to hardware, software must first write the appropriate fields in this register, and then issue the appropriate page- selective invalidate command thro ugh the iotlb_reg. hardware ignores bits 63: n, where n is the maximum guest address width (mgaw) supported. 11:7 ro 0h reserved (rsvd) 6rw 0huncore invalidation hint (ih) the field provides hint to hardware about preserving or flushing the non-leaf (page-directory) entries that may be cached in hardware: 0 = software may have modified both leaf and non-leaf page- table entries corresponding to mappings specified in the addr and am fields. on a page-selective invalidation request, hardware must flush both the cached leaf and non- leaf page-table entries corre sponding to the mappings specified by addr and am fields. 1 = software has not modified any non-leaf page-table entries corresponding to mappings sp ecified in the addr and am fields. on a page-selective in validation request, hardware may preserve the cached non-leaf page-table entries corresponding to mappings spec ified by addr and am fields. 5:0 rw 00h uncore address mask (am) the value in this field specifies the number of low order bits of the addr field that must be masked for the invalidation operation. this field enables software to request invalidation of contiguous mappings for size-aligned regions. for example: mask addr bits pages value masked invalidated 0 none 1 1 12 2 2 13:12 4 3 14:12 8 4 15:12 16 when invalidating mappings for super-pages, software must specify the appropriate mask value. for example, when invalidating mapping for a 2 mb page, software must specify an address mask value of at least 9. hardware implementations report the maximum supported mask value through the capability register. processor configuration registers 300 datasheet, volume 2 2.18.29 iotlb_reg?iotlb invalidate register this register invalidates iotlb. the act of writing the upper byte of the iotlb_reg with ivt field set causes the hardware to perform the iotlb invalidation. b/d/f/type: 0/0/0/gfxvtbar address offset: 108?10fh reset value: 0200000000000000h access: ro-v, rw, rw-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63 rw-v 0h uncore invalidate iotlb (ivt) software requests iotlb invalidation by setting this field. software must also set the requested invalidation granularity by programming the iirg field. hardware clears the ivt field to indicate the invalidation request is complete. hardware also indica tes the granularity at which the invalidation operation was performed through the iaig field. software must not submit another invalidation request through this register while the ivt field is set, nor update the associated invalidate address register. software must not submit iotl b invalidation requests when there is a context-cache invalid ation request pending at this remapping hardware unit. hardware implementations reporting write-buffer flushing requirement (rwbf=1 in capabili ty register) must implicitly perform a write buffer flushing before invalidating the iotlb. 62:62 ro 0h reserved (rsvd) 61:60 rw 0h uncore iotlb invalidation request granularity (iirg) when requesting hardware to invalidate the iotlb (by setting the ivt field), software writes the requested invalidation granularity through this field. the following are the encodings for the field. 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalidatio n request. the target domain- id must be specified in the did field. 11 = page-selective invalidation request. the target address, mask and invalidation hint must be specified in the invalidate address register, and the domain-id must be provided in the did field. hardware implementations may pr ocess an invalidation request by performing invalidation at a coarser granularity than requested. hardware indicates completion of the invalidation request by clearing the ivt field. at this time, the granularity at which actual invalidation was performed is reported through the iaig field 59:59 ro 0h reserved (rsvd) datasheet, volume 2 301 processor configuration registers 58:57 ro-v 1h uncore iotlb actual invalidation granularity (iaig) hardware reports the granularity at which an invalidation request was processed through this fiel d when reporting invalidation completion (by clearing the ivt field). the following are the encodings for this field. 00 = reserved. this indicates hardware detected an incorrect invalidation request and ignored the request. examples of incorrect invalidation reques ts include detecting an unsupported address mask va lue in invalidate address register for page-selective invalidation requests. 01 = global invalidation performed. this could be in response to a global, domain-selective, or page-selective invalidation request. 10 = domain-selective invalidatio n performed using the domain- id specified by software in the did field. this could be in response to a domain-selective or a page-selective invalidation request. 11 = domain-page-selective invalidation performed using the address, mask and hint specified by software in the invalidate address register and domain-id specified in did field. this can be in response to a page-selective invalidation request. 56:50 ro 0h reserved (rsvd) 49 rw 0b uncore drain reads (dr) this field is ignored by hardware if the drd field is reported as clear in the capability register. when the drd field is reported as set in the capability register , the following encodings are supported for this field: 0 = hardware may complete the iotlb invalidation without draining any translated dma read requests. 1 = hardware must drain dma read requests. 48 rw 0b uncore drain writes (dw) this field is ignored by hardware if the dwd field is reported as clear in the capability register. when the dwd field is reported as set in the capability regist er, the following encodings are supported for this field: 0 = hardware may complete the iotlb invalidation without draining dma write requests. 1 = hardware must drain relevant translated dma write requests. 47:40 ro 0h reserved (rsvd) 39:32 rw 00h uncore domain-id (did) this field indicates the id of the domain whose iotlb entries need to be selectively inva lidated. this field must be programmed by software for domain-selective and page-selective invalidation requests. the capability register reports th e domain-id width supported by hardware. software must ensure that the value written to this field is within this limit. hard ware ignores and not implements bits 47:(32+n), where n is the supported domain-id width reported in the capability register. 31:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/gfxvtbar address offset: 108?10fh reset value: 0200000000000000h access: ro-v, rw, rw-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description processor configuration registers 302 datasheet, volume 2 2.18.30 frcdl_reg?fault recording low register this register records fault information when primary fault logging is active. hardware reports the number and location of fault recording registers through the capability register. this register is relevant only for primary fault logging. this register is sticky and can be cleared on ly through power good reset or by software clearing the rw1c fields by writing a 1. b/d/f/type: 0/0/0/gfxvtbar address offset: 200?207h reset value: 0000000000000000h access: ros-v size: 64 bits bios optimal default 0000000000000000h bit access reset value rst/ pwr description 63:12 ros-v 00000000 00000h powergood fault info (fi) when the fault reason (fr) field indicates one of the dma- remapping fault conditions, bits 63:12 of this field contain the page address in the faulted dma request. hardware treats bits 63:n as reserved (0), where n is the maximum guest address width (mgaw) supported. when the fault reason (fr) field indicates one of the interrupt- remapping fault conditions, bits 63:48 of this field indicate the interrupt_index computed for the faulted interrupt request, and bits 47:12 are cleared. this field is relevant only when the f field is set. 11:0 ro 0h reserved (rsvd) datasheet, volume 2 303 processor configuration registers 2.18.31 frcdh_reg?fault recording hi gh register this register records fault information when primary fault logging is active. hardware reports the number and location of fault recording registers through the capability register. this register is relevant only for primary fault logging. this register is sticky and can be cleared on ly through power good reset or by software clearing the rw1c fields by writing a 1. b/d/f/type: 0/0/0/gfxvtbar address offset: 208?20fh reset value: 0000000000000000h access: ro, rw1cs, ros-v size: 64 bits bios optimal default 0000000000000000h bit access reset value rst/ pwr description 63 rw1cs 0b powergood fault (f) hardware sets this field to indicate a fault is logged in this fault recording register. the f field is set by hardware after the details of the fault is recorded in other fields. when this field is set, hardware may collapse additional faults from the same source-id (sid). software writes the value read from this field to clear it. 62 ros-v 0b powergood type (t) type of the faulted request: 0 = write request 1 = read request or atomicop request this field is relevant only when the f field is set, and when the fault reason (fr) indicates one of the dma-remapping fault conditions. 61:60 ro 00b uncore address type (at) this field captures the at field from the faulted dma request. hardware implementations not supporting device-iotlbs (di field clear in extended capability register) treat this field as rsvdz. when supported, this field is valid only when the f field is set, and when the fault reason (fr) indicates one of the dma- remapping fault conditions. 59:40 ro 0h reserved (rsvd) 39:32 ros-v 00h powergood fault reason (fr) this field provides the reason for the fault. this field is relevant only when the f field is set. 31:16 ro 0h reserved (rsvd) 15:0 ros-v 000000000 0000000b powergood source identifier (sid) this field provides the requeste r-id associated with the fault condition. this field is relevant only when the f field is set. processor configuration registers 304 datasheet, volume 2 2.18.32 vtpolicy?dma remap engi ne policy control register this register contains all the policy bits related to the dma remap engine. b/d/f/type: 0/0/0/gfxvtbar address offset: ff0?ff3h reset value: 00000000h access: rw-l, ro, ro-kfw, rw-kl size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31 rw-kl 0b uncore dma remap engine policy lock-down (dmar_lckdn) this register bit protects all th e dma remap engine specific policy configuration registers. once this bit is set by software all the dma remap engine registers within the range f00h to ffch will be read-only. this bit can only be clear through platform reset. 30:0 ro 0h reserved (rsvd) datasheet, volume 2 305 processor configuration registers 2.19 pcu mchbar registers table 2-22. pcu mchbar register address map address offset register symbol register name reset value access 0?587fh rsvd reserved ? ? 5880?5883h mem_trml_esti mation_config memory thermal estimation configuration ca9171e7h rw 5884?5887h rsvd reserved 00000000h rw 5888?588bh mem_trml_thre sholds_config memory thermal thresholds configuration 00e4dad0h rw 588c?589fh rsvd reserved ? ? 58a0?58a3h mem_trml_stat us_report memory thermal status report 00000000h ro-v 58a4?58a7h mem_trml_temp erature_report memory thermal temperature report 00000000h ro-v 58a8?58abh mem_trml_inter rupt memory thermal interrupt 00000000h rw 58ac?5947h rsvd reserved ? ? 5948?594bh gt_perf_status gt performance status 00000000h ro-v 594c?5993h rsvd reserved ? ? 5994?5997h rp_state_limits rp-state limitations 000000ffh rw 5998?599bh rp_state_cap rp state capability 00000000h ro-fw 599c?5c1fh rsvd reserved ? ? 5c20?5c23h pcu_mmio_freq _clipping_caus e_status pcu mmio frequency clipping cause status 00000000h rw 5c24?5c27h pcu_mmio_freq _clipping_caus e_log pcu mmio frequency clipping cause log 00000000h rw 5c28?5d0fh rsvd reserved ? ? 5d10?5d17h sskpd sticky scratchpad data 00000000000 00000h rws, rw 5d18?5f03h rsvd reserved ? ? processor configuration registers 306 datasheet, volume 2 2.19.1 mem_trml_estima tion_config?memory thermal estimation configuration register this register contains configuration regard ing vts temperature estimation calculations that are done by pcode. b/d/f/type: 0/0/0/mchbar pcu address offset: 5880?5883h reset value: ca9171e7h access: rw size: 32 bits bios optimal default ca9171e7h bit access reset value rst/ pwr description 31:22 rw 10eh uncore vts multiplier (vts_multiplier) the vts multiplier serves as a mu ltiplier for the translation of the memory bw to temperature. the units are given in 1 / power(2,44). 21:12 rw 0c8h uncore vts time constant (vts_time_constant) this factor is relevant only fo r bw based temperature estimation. it is equal to "1 minus alpha". the value of the time constant (1 ? alpha) is determined by vts_time_constant / power(2,25) per 1 msec. 11 ro 0h reserved (rsvd) 10:4 rw 32h uncore vts offset adder (vts_offset) the offset is intended to provide a temperature proxy offset, so the option of having a fixed adder to vts output is available. 3ro 0h reserved (rsvd) 2rw 1buncore disable extts# (disable_extts) when set, the processo r will ignore the extts# signal status that it receives from the pch through pm_sync messaging. 0 = enable 1 = disable 1rw 0buncore disable virtual temperature sensor (disable_vts) when set, the processor will ignore the vts. 0 = enable 1 = disable 0rw 0buncore disable peci injected temperature (disable_peci_inject_temp) when set, the processor will ignore any dram temperature written to it over the peci bus. 0 = enable 1 = disable datasheet, volume 2 307 processor configuration registers 2.19.2 mem_trml_thresholds_config?memory thermal thresholds co nfiguration register this register is used to describe the thre sholds of the memory thermal management in the memory controller. the warm threshold defi nes when self-refresh is at double data rate. throttling can also be applied at this threshold based on the configuration in the memory controller. the hot threshold defines the threshold at which severe thermal throttling will occur. self refresh is also at double rate during a hot condition. b/d/f/type: 0/0/0/mchbar pcu address offset: 5888?588bh reset value: 00e4dad0h access: rw size: 32 bits bios optimal default 00edad0h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15 rw 1b uncore hot threshold enable (hot_threshold_enable) this bit must be set to allow the hot threshold. 14:8 rw 1010101b uncore hot threshold (hot_threshold) this threshold defines what is the acceptable temperature limitation. when this threshold is crossed, severe throttling takes place. the self refresh is also at double rate. 7rw 1buncore warm threshold enable (warm_threshold_enable) this bit must be set to allow the warm threshold. 6:0 rw 1010000b uncore warm threshold (warm_threshold) the warm temperature threshold defines when the self refresh is at double rate. throttling can also be applied at this threshold based on the configuration in the memory controller. processor configuration registers 308 datasheet, volume 2 2.19.3 mem_trml_status_report?memory thermal status report register this register reports the thermal status of dram. b/d/f/type: 0/0/0/mchbar pcu address offset: 58a0?58a3h reset value: 00000000h access: ro-v size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:25 ro 0h reserved (rsvd) 24 ro-v 0b uncore double self refresh (dsr) 0 = normal self refresh 1 = double self refresh 23:16 ro-v 00h uncore reserved (rsvd) 15:8 ro-v 00h uncore channel 1 status (channel1_status) the format is for each channel and is defined as follows: 00 = cold 01 = warm 11 = hot bits 8:9: rank 0 channel 1 bits 10:11: rank 1 channel 1 bits 12:13: rank 2 channel 1 bits 14:15: rank 3 channel 1 7:0 ro-v 00h uncore channel 0 status (channel0_status) the format is for each channel and is defined as follows: 00 = cold 01 = warm 11 = hot bits 0:1: rank 0 channel 0 bits 2:3: rank 1 channel 0 bits 4:5: rank 2 channel 0 bits 6:7: rank 3 channel 0 datasheet, volume 2 309 processor configuration registers 2.19.4 mem_trml_temperature_report?memory thermal temperature report register this register is used to report the thermal status of the memory. the channel max temperature field is used to report the maximal temperature of all ranks. 2.19.5 mem_trml_interrupt?memory thermal interrupt register hardware uses this information to determin e whether a memory thermal interrupt is to be generated or not. b/d/f/type: 0/0/0/mchbar pcu address offset: 58a4?58a7h reset value: 00000000h access: ro-v size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 0h reserved (rsvd) 23:16 ro-v 00h uncore reserved (rsvd) 15:8 ro-v 00h uncore channel 1 maximum temperature (channel1_max_temperature) temperature in degrees c. 7:0 ro-v 00h uncore channel 0 maximum temperature (channel0_max_temperature) temperature in degrees c. b/d/f/type: 0/0/0/mchbar pcu address offset: 58a8?58abh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:5 ro 0h reserved (rsvd) 4rw 0b reserved (rsvd) 3ro 0h reserved (rsvd) 2rw 0buncore hot threshold interrupt enable (hot_threshold_int_enable) this bit controls the generation of a thermal interrupt whenever the hot threshold temperature is crossed. 1ro 0h reserved (rsvd) 0rw 0buncore warm threshold interrupt enable (warm_threshold_int_enable) this bit controls the generation of a thermal interrupt whenever the warm threshold temperature is crossed. processor configuration registers 310 datasheet, volume 2 2.19.6 gt_perf_status?gt pe rformance status register this register provides the p-state encoding for the secondary power plane?s current pll frequency and the current vid. 2.19.7 rp_state_limits?rp-state limitations register this register allows software to limit the maximum base frequency for the integrated graphics engine (gt) allowed during run-time. b/d/f/type: 0/0/0/mchbar pcu address offset: 5948?594bh reset value: 00000000h access: ro-v size: 32 bits bios optimal default 0000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:8 ro-v 00h uncore rp-state ratio (rp_state_ratio) this field provides the ratio of the current rp-state. 7:0 ro-v 00h reserved (rsvd) b/d/f/type: 0/0/0/mchbar pcu address offset: 5994?5997h reset value: 000000ffh access: rw size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:0 rw ffh uncore rp-state limit (rpstt_lim) this field indicates the maximu m base frequency limit for the integrated graphics engine (gt) allowed during run-time. datasheet, volume 2 311 processor configuration registers 2.19.8 rp_state_cap?rp st ate capability register this register contains the maximum base frequency capability for the integrated graphics engine (gt). 2.19.9 pcu_mmio_freq_clippi ng_cause_status register this register provides the status of the frequency clipping cause in mmio for both power plane 0 (ia) and power plane 1 (gt) b/d/f/type: 0/0/0/mchbar pcu address offset: 5998?599bh reset value: 00000000h access: ro-fw size: 32 bits bios optimal default 00h bit access reset value rst/ pwr description 31:24 ro 0h reserved (rsvd) 23:16 ro-fw 00h uncore rpn capability (rpn_cap) this field indicates the maximum rpn base frequency capability for the integrated graphics engine (gt). values are in units of 100 mhz. 15:8 ro-fw 00h uncore rp1 capability (rp1_cap): this field indicates the maximum rp1 base frequency capability for the integrated graphics engine (gt). values are in units of 100 mhz. 7:0 ro-fw 00h uncore rp0 capability (rp0_cap): this field indicates the maximum rp0 base frequency capability for the integrated graphics engine (gt). values are in units of 100 mhz. b/d/f/type: 0/0/0/mchbar pcu address offset: 5c20?5c23h reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31 rw 00000000h uncore pp1_clipped set if the pp1 (gt) frequency requested was clipped. 30 rw 00000000h reserved (rsvd) 29 rw 00000000h uncore pp1_clipped_non_turbo set if the pp1 (gt) frequency requested was clipped, but current frequency is lower than rp1 (max_non_turbo). 28:25 rw 00000000h reserved (rsvd) 24 rw 00000000h uncore pp1_clipped_edp set if the pp1 (gt) frequency re quested was clipped by edp limit (vmax, iccmax, reliability, and so on). 23 rw 00000000h reserved (rsvd) 22 rw 00000000h uncore pp1_clipped_hot_vr set if the pp1 (gt) frequency requested was clipped by hot indication from vr on svid. 21 rw 00000000h uncore p1_clipped_pl2 set if the pp1 (gt) frequency requested was clipped by pl2 (power_limit_2) power limiting algorithm. processor configuration registers 312 datasheet, volume 2 20:19 rw 00000000h reserved (rsvd) 18 rw 00000000h uncore pp1_clipped_pl1 set if the pp1 (gt) frequency requested was clipped by pl1 (power_limit_1) power limiting algorithm. 17 rw 00000000h uncore pp1_clipped_thermals set if the pp1 (gt) frequency re quested was clipped by internal thermal throttling algorithm. 16 rw 00000000h uncore pp1_clipped_ext_prochot set if the pp1 (gt) frequency re quested was clipped by external prochot indication. 15 rw 00000000h uncore pp0_clipped set if the pp0 (ia) frequency requested by the operating system was clipped. 14 rw 00000000h uncore pp0_clipped_n_core_turbo set if the pp0 (ia) frequency requested by the operating system was clipped, but current frequency is lower than max_turbo[n- cores]. 13 rw 00000000h uncore pp0_clipped_non_turbo set if the pp0 (ia) frequency requested by the operating system was clipped, but current frequency is lower than max_non_turbo. 12:9 rw 00000000h reserved (rsvd) 8 rw 00000000h uncore pp0_clipped_edp set if the pp0 (ia) frequency requested by the operating system was clipped by edp limit (vmax, iccmax, reliability, and so on) 7 rw 00000000h uncore pp0_clipped_mct set if the pp0 (ia) frequency requested by the operating system was clipped by multi core turbo demotion algorithm. 6 rw 00000000h uncore pp0_clipped_hot_vr set if the pp0 (ia) frequency requested by the operating system was clipped by hot indication from vr on svid. 5 rw 00000000h uncore pp0_clipped_pl2 set if the pp0 (ia) frequency requested by the operating system was clipped by pl2 (power_limit_2) power limiting algorithm. 4 rw 00000000h uncore pp0_clipped_gt_driver set if the pp0 (ia) frequency requested by the operating system was clipped by gt driver. 3 rw 00000000h reserved (rsvd) 2 rw 00000000h uncore pp0_clipped_pl1 set if the pp0 (ia) frequency requested by the operating system was clipped by pl1 (power_limit_1) power limiting algorithm. 1 rw 00000000h uncore pp0_clipped_thermals set if the pp0 (ia) frequency requested by the operating system was clipped by internal th ermal throttling algorithm. 0 rw 00000000h uncore pp0_clipped_ext_prochot set if the pp0 (ia) frequency requested by the operating system was clipped by external prochot indication. b/d/f/type: 0/0/0/mchbar pcu address offset: 5c20?5c23h reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description datasheet, volume 2 313 processor configuration registers 2.19.10 pcu_mmio_freq_clipping_cause_log register this register is the log of the frequency clipping cause in mmio for both power plane 0 (ia) and power plane 1 (gt). the bit definitions are the same as in pcu_mmio_freq_clipping_cau se_status register; the processor will constantly ?or? in the status to give a log of any clipping since the last clear. software can clear the log by writing zeros to this register. note: there is no assurance of atomicity of soft ware read-clear and hardware read-modify- write; thus, there is a small chance of misreporting. b/d/f/type: 0/0/0/mchbar pcu address offset: 5c24-5c27h default value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31 rw 00000000h uncore pp1_clipped set if the pp1 (gt) freque ncy requested was clipped. 30 rw 00000000h reserved (rsvd) 29 rw 00000000h uncore pp1_clipped_non_turbo set if the pp1 (gt) freque ncy requested was clipped, but current frequency is lower than rp1 (max_non_turbo). 28:25 rw 00000000h reserved (rsvd) 24 rw 00000000h uncore pp1_clipped_edp set if the pp1 (gt) frequency requested was clipped by edp limit (vmax, iccmax, reliability, and so on). 23 rw 00000000h reserved (rsvd) 22 rw 00000000h uncore pp1_clipped_hot_vr set if the pp1 (gt) frequency requested was clipped by hot indication from vr on svid. 21 rw 00000000h uncore p1_clipped_pl2 set if the pp1 (gt) frequency requested was clipped by pl2 (power_limit_2) power limiting algorithm. 20-19 rw 00000000h reserved (rsvd) 18 rw 00000000h uncore pp1_clipped_pl1 set if the pp1 (gt) frequency requested was clipped by pl1 (power_limit_1) power limiting algorithm. 17 rw 00000000h uncore pp1_clipped_thermals set if the pp1 (gt) frequency requested was clipped by internal thermal throttling algorithm. 16 rw 00000000h uncore pp1_clipped_ext_prochot set if the pp1 (gt) frequency requested was clipped by external prochot indication. 15 rw 00000000h uncore pp0_clipped set if the pp0 (ia) frequency requested by os was clipped. 14 rw 00000000h uncore pp0_clipped_n_core_turbo set if the pp0 (ia) frequency requested by os was clipped, but current frequency is lower than max_turbo[n-cores]. processor configuration registers 314 datasheet, volume 2 13 rw 00000000h uncore pp0_clipped_non_turbo set if the pp0 (ia) frequency requested by os was clipped, but current frequency is lower than max_non_turbo. 12:9 rw 00000000h reserved (rsvd) 8 rw 00000000h uncore pp0_clipped_edp set if the pp0 (ia) frequency requested by os was clipped by edp limit (vmax, iccmax, reliability, and so on). 7 rw 00000000h uncore pp0_clipped_mct set if the pp0 (ia) frequency requested by os was clipped by multi core turbo demotion algorithm. 6 rw 00000000h uncore pp0_clipped_hot_vr set if the pp0 (ia) frequency requested by os was clipped by hot indication from vr on svid. 5 rw 00000000h uncore pp0_clipped_pl2 set if the pp0 (ia) frequency requested by os was clipped by pl2 (power_limit_2) power limiting algorithm. 4 rw 00000000h uncore pp0_clipped_gt_driver set if the pp0 (ia) frequency requested by os was clipped by gt driver. 3 rw 00000000h reserved (rsvd) 2 rw 00000000h uncore pp0_clipped_pl1 set if the pp0 (ia) frequency requested by os was clipped by pl1 (power_limit_1) power limiting algorithm. 1 rw 00000000h uncore pp0_clipped_thermals set if the pp0 (ia) frequency requested by os was clipped by internal ther mal throttling algorithm. 0 rw 00000000h uncore pp0_clipped_ext_prochot set if the pp0 (ia) frequency requested by os was clipped by external prochot indication. b/d/f/type: 0/0/0/mchbar pcu address offset: 5c24-5c27h default value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description datasheet, volume 2 315 processor configuration registers 2.19.11 sskpd?sticky scra tchpad data register this register holds 64 writable bits with no functionality behind them. it is for the convenience of bios and graphics drivers. b/d/f/type: 0/0/0/mchbar pcu address offset: 5d10?5d17h reset value: 0000000000000000h access: rws, rw size: 64 bits bit access reset value rst/ pwr description 63:32 rws 00000000h powergood scratchpad data (skpd ) 2 words of data storage. 31:30 rws 00b powergood reserved for future use (rwsvd3) bit 30 controls the way bios calculate wm3 value. bit 31 is reserved for future use. 29:24 rws 00h powergood ddrio power down shutdown latency time (wm3) number of microseconds to access memory if memory is in self refresh (sr) with ddrio in power down (epg mode) (0.5 us granularity). 00h = 0 us 01h = 0.5 us 02h = 1 us ... 3fh = 31.5 us note: the value in this field corresponds to the memory latency requested to the display engine when memory pll shutdown is enabled. the display lp3 latency and watermark values (gttmmadr offset 45110h) should be programmed to match the latency in this register. 23 rws 0b powergood reserved for future use (rwsvd2) reserved for future use 22 rw 0b uncore mpll fast lock disable (mpll_fast_dis) copy of cr pcu [sbpll_fast_dis] 21:16 rws 000000b powergood mpll shutdown latency time (wm2) number of microseconds to access memory if the mpll is shutdown (requires memory in self refresh). the value is programmed in 0.5 us granularity. 00h = 0 us 01h = 0.5 us 02h = 1 us ... 3fh = 31.5 us note: the value in this field corresponds to the memory latency requested to the display engine when mpll shutdown is enabled. the display lp2 latency and watermark values (gttmmadr offset 4510ch) should be programmed to match the latency in this register. 15:14 rws 00b powergood reserved for future use (rwsvd1) reserved for future use processor configuration registers 316 datasheet, volume 2 13:8 rws 000000b powergood self refresh and mdll latency time (wm1) this field provides the number of microseconds to access memory if memory is in self refresh and mdll is turned off (0.5 us granularity). 00h = 0 us 01h = 0.5 us 02h = 1 us ... 3fh = 31.5 us note: the value in this field co rresponds to the memory latency requested to the display engine when memory is in self refresh. th e display lp1 latency and watermark values (gttmmadr offset 45108h) should be programmed to match the latency in this register. 7:6 rws 00b powergood reserved for future use (rwsvd0) reserved for future use 5:0 rws 000000b powergood normal latency time (wm0) this field provides the number of microseconds to access memory for normal memory operations (0.1 us granularity). 00h = 0 us 01h = 0.1 us 02h = 0.2 us ... 3fh = 6.3 us note: for the processor, the worst-case latency is 0.6 us. wm0 latency is the sum of: ? partial intel high definition audio request in front of the display request = 100 ns ? refresh just in front of the intel high definition audio request = 300 ns ? maintenance (zqcal + some clocks) = 130 ns (ddr 1067) to 80 ns (ddr 1600) ? activate = 15 ns ? cas = 15 ns ? sa roundtrip = ~15 ns total: 525 ns (ddr 1600) ? 575 ns (ddr 1067) b/d/f/type: 0/0/0/mchbar pcu address offset: 5d10?5d17h reset value: 0000000000000000h access: rws, rw size: 64 bits bit access reset value rst/ pwr description datasheet, volume 2 317 processor configuration registers 2.20 pxpepbar registers 2.20.1 epvc0rctl?ep vc 0 re source control register this register controls the resources associated with egress port virtual channel 0. table 2-23. pxpepbar address map address offset register symbol register name reset value access 0?13h rsvd reserved 0h ro 14?17h epvc0rctl ep vc 0 resource control 800000ffh ro, rw 18?9fh rsvd reserved ? ? b/d/f/type: 0/0/0/pxpepbar address offset: 14?17h reset value: 800000ffh access: ro, rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 ro 0h reserved (rsvd) 19:17 rw 000b uncore port arbitration select (pas) this field configures the vc resource to provide a particular port arbitration service. the value of 0h corresponds to the bit position of the only asserted bit in the port arbitration capability field. 16:0 ro 0h reserved (rsvd) processor configuration registers 318 datasheet, volume 2 2.21 default peg/dmi vtd remapping engine registers table 2-24. default peg/dmi vtd remapping en gine register addre ss map (sheet 1 of 2) address offset symbol register name reset value access 0?3h ver_reg version register 00000010h ro 4?7h rsvd reserved 0h ro 8?fh cap_reg capability register 00c9008020660 262h ro 10?17h ecap_reg extended capability register 0000000000f01 0dah ro-v, ro 18?1bh gcmd_reg global command register 00000000h ro, wo 1c?1fh gsts_reg global status register 00000000h ro, ro-v 20?27h rtaddr_reg root-entry table address register 0000000000000 000h rw 28?2fh ccmd_reg context command register 0000000000000 000h rw-v, rw, ro-v 30?33h rsvd reserved 0h ro 34?37h fsts_reg fault status register 00000000h rw1cs, ros-v, ro 38?3bh fectl_reg fault event control register 80000000h rw, ro-v 3c?3fh fedata_reg fault event data register 00000000h rw 40?43h feaddr_reg fault event address register 00000000h rw 44?47h feuaddr_reg fault event upper address register 00000000h rw 48?57h rsvd reserved 0h ro 58?5fh aflog_reg advanced fault log register 0000000000000 000h ro 60?63h rsvd reserved 0h ro 64?67h pmen_reg protected memory enable register 00000000h rw, ro-v 68?6bh plmbase_reg protected low-memory base register 00000000h rw 6c?6fh plmlimit_reg protected low-memory limit register 00000000h rw 70?77h phmbase_reg protected high-memory base register 0000000000000 000h rw 78?7fh phmlimit_reg protected high-memory limit register 0000000000000 000h rw 80?87h iqh_reg invalidation queue head register 0000000000000 000h ro-v 88?8fh iqt_reg invalidation queue tail register 0000000000000 000h rw-l 90?97h iqa_reg invalidation queue address register 0000000000000 000h rw-l 98?9bh rsvd reserved 0h ro 9c?9fh ics_reg invalidation completion status register 00000000h rw1cs a0?a3h iectl_reg invalidation event control register 80000000h rw-l, ro-v a4?a7h iedata_reg invalidation event data register 00000000h rw-l a8?abh ieaddr_reg invalidation event address register 00000000h rw-l datasheet, volume 2 319 processor configuration registers 2.21.1 ver_reg?version register this register reports the architecture vers ion supported. backward compatibility for the architecture is maintained with new revision numbers, allowing software to load remapping hardware drivers written for prior architecture versions. ac?afh ieuaddr_reg invalidation event upper address register 00000000h rw-l b0?b7h rsvd reserved 0h ro b8?bfh irta_reg interrupt remapping table address register 0000000000000 000h rw-l c0?ffh rsvd reserved 0h ro 100?107h iva_reg invalidate address register 0000000000000 000h rw 108?10fh iotlb_reg iotlb invalidate register 0000000000000 000h rw, rw-v, ro-v 110?ff3h rsvd reserved ? ? table 2-24. default peg/dmi vtd remapping en gine register addres s map (sheet 2 of 2) address offset symbol register name reset value access b/d/f/type: 0/0/0/vc0premap address offset: 0?3h reset value: 00000010h access: ro size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31:8 ro 0h reserved (rsvd) 7:4 ro 0001b uncore major version number (max) this field indicates supported architecture version. 3:0 ro 0000b uncore minor version number (min) this bit indicates supported architecture minor version. processor configuration registers 320 datasheet, volume 2 2.21.2 cap_reg?capability register this register reports general remapping hardware capabilities. b/d/f/type: 0/0/0/vc0premap address offset: 8?fh reset value: 00c9008020660262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description 63:56 ro 0h reserved (rsvd) 55 ro 1b uncore dma read draining (drd) 0 = hardware does not support draining of dma read requests. 1 = hardware supports draining of dma read requests. 54 ro 1b uncore dma write draining (dwd) 0 = hardware does not support draining of dma write requests. 1 = hardware supports draining of dma write requests. 53:48 ro 001001b uncore maximum address mask value (mamv) the value in this field indicate s the maximum supported value for the address mask (am) field in the invalidation address register (iva_reg) and iotlb invalidation descriptor (iotlb_inv_dsc). this field is valid only when the ps i field in capability register is reported as set. 47:40 ro 00000000 b uncore number of fault-recording registers (nfr) the number of fault recording registers is computed as n+1, where n is the value reported in this field. implementations must support at least one fault recording register (nfr = 0) for each remapping hardware unit in the platform. the maximum number of fault recording registers per remapping hardware unit is 256. 39 ro 1b uncore page selective invalidation (psi) 0 = hardware supports only domain and global invalidates for iotlb 1 = hardware supports page selective, domain and global invalidates for iotlb. hardware implementations reporting this field as set are recommended to support a maximum address mask value (mamv) value of at least 9. 38:38 ro 0h reserved (rsvd) 37:34 ro 0000b uncore super-page support (sps) this field indicates the super page sizes supported by hardware. a value of 1 in any of these bits indicates the corresponding super-page size is supported. the super-page sizes corresponding to various bit positions within this field are: 0 = 21-bit offset to page frame (2 mb) 1 = 30-bit offset to page frame (1 gb) 2 = 39-bit offset to page frame (512 gb) 3 = 48-bit offset to page frame (1 tb) hardware implementations supporting a specific super-page size must support all smaller super-page sizes; that is, only valid values for this field are 0001b, 0011b, 0111b, 1111b. datasheet, volume 2 321 processor configuration registers 33:24 ro 020h uncore fault-recording register offset (fro) this field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the fi rst fault recording register is calculated as x+(16*y). 23 ro 0b uncore isochrony (isoch) 0 = remapping hardware unit has no critical isochronous requesters in its scope. 1 = remapping hardware unit has one or more critical isochronous requesters in its scope. to ensure isochronous performance, software must ensure invalidation operations do not impact active dma streams from such requesters. this implies, when dma is active, software performs page- selective invalidations (and not coarser invalidations). 22 ro 1b uncore zero length read (zlr) 0 = indicates the remapping hardware unit blocks (and treats as fault) zero length dma read requests to write-only pages. 1 = indicates the remapping hardwa re unit supports zero length dma read requests to write-only pages. dma remapping hardware implementations are recommended to report zlr field as set. 21:16 ro 100110b uncore maximum guest address width (mgaw) this field indicates the maximum dma virtual addressability supported by remapping hardware. the maximum guest address width (mgaw) is computed as (n+1), where n is the value reported in this field. for example, a hardware implementation supporting 48-bit mgaw reports a value of 47 (101111b) in this field. if the value in this field is x, untranslated and translated dma requests to addresses above 2^(x+1)-1 are always blocked by hardware. translations requests to address above 2^(x+1)-1 from allowed devices return a null translation completion data entry with r=w=0. guest addressability for a given dma request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structure. (adjusted guest address widths supported by hardware are reported through the sagaw field). implementations are recommended to support mgaw at least equal to the physical addressab ility (host address width) of the platform. 15:13 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: 8?fh reset value: 00c9008020660262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description processor configuration registers 322 datasheet, volume 2 12:8 ro 00010b uncore supported adjusted guest address widths (sagaw) this 5-bit field indicates the supported adjusted guest address widths (which in turn represents the levels of page-table walks for the 4 kb base page size) supported by the hardware implementation. a value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. the adjusted guest address widths corresponding to va rious bit positions within this field are: 0 = 30-bit agaw (2-level page table) 1 = 39-bit agaw (3-level page table) 2 = 48-bit agaw (4-level page table) 3 = 57-bit agaw (5-level page table) 4 = 64-bit agaw (6-level page table) software must ensure that th e adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field. 7ro 0buncore caching mode (cm) 0 = not-present and erroneous entries are not cached in any of the remapping caches. invalidat ions are not required for modifications to individual not present or invalid entries. however, any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective. 1 = not-present and erroneous mappings may be cached in the remapping caches. any software updates to the remapping structures (including updates to "not-present" or erroneous entries) require ex plicit invalidation. hardware implementations of this architecture must support a value of 0 in this field. 6ro 1buncore protected high-memory region (phmr) 0 = indicates protected high-memory region is not supported. 1 = indicates protected high-memory region is supported. 5ro 1buncore protected low-memory region (plmr) 0 = protected low-memory region is not supported. 1 = protected low-memory region is supported. b/d/f/type: 0/0/0/vc0premap address offset: 8?fh reset value: 00c9008020660262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description datasheet, volume 2 323 processor configuration registers 4ro 0buncore required write-buffer flushing (rwbf) 0 = indicates no write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware. 1 = indicates software must explicitly flush the write buffers to ensure updates made to memory-resident remapping structures are visible to hardware. 3ro 0buncore advanced fault logging (afl) 0 = advanced fault logging is not supported. only primary fault logging is supported. 1 = advanced fault logging is supported. 2:0 ro 010b uncore number of domains supported (nd) 000 = hardware supports 4-bit domain-ids with support for up to 16 domains. 001 = hardware supports 6-bit domain-ids with support for up to 64 domains. 010 = hardware supports 8-bit domain-ids with support for up to 256 domains. 011 = hardware supports 10-bit domain-ids with support for up to 1024 domains. 100 = hardware supports 12-bit domain-ids with support for up to 4k domains. 100 = hardware supports 14-bit domain-ids with support for up to 16k domains. 110 = hardware supports 16-bit domain-ids with support for up to 64k domains. 111 = reserved. b/d/f/type: 0/0/0/vc0premap address offset: 8?fh reset value: 00c9008020660262h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description processor configuration registers 324 datasheet, volume 2 2.21.3 ecap_reg?extended capability register this register reports remapping hardware extended capabilities. b/d/f/type: 0/0/0/vc0premap address offset: 10?17h reset value: 0000000000f010dah access: ro-v, ro size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description 63:24 ro 0h reserved (rsvd) 23:20 ro 1111b uncore maximum handle mask value (mhmv) the value in this field indicate s the maximum supported value for the handle mask (hm) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc). this field is valid only when the ir field in extended capability register is reported as set. 19:18 ro 0h reserved (rsvd) 17:8 ro 010h uncore iotlb register offset (iro) this field specifies the offset to the iotlb registers relative to the register base address of this remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the fi rst iotlb invalidation register is calculated as x+(16*y). 7ro-v 1b uncore snoop control (sc) 0 = hardware does not support 1-setting of the snp field in the page-table entries. 1 = hardware supports the 1-setti ng of the snp field in the page-table entries. 6ro-v 1b uncore pass through (pt) 0 = hardware does not support pass-through translation type in context entries. 1 = hardware supports pass-through translation type in context entries. 5ro 0buncore caching hints (ch) 0 = hardware does not support iotlb caching hints (alh and eh fields in context-entries are treated as reserved). 1 = hardware supports ioltb caching hints through the alh and eh fields in context-entries. 4ro 0h reserved (rsvd) 3ro-v 1b uncore interrupt remapping support (ir) 0 = hardware does not support interrupt remapping. 1 = hardware supports interrupt remapping. implementations reporting this field as set must also support queued invalidation (qi). 2ro 0buncore device iotlb support (di) 0 = hardware does not support device-iotlbs. 1 = hardware supports device-iotlbs. implementations reporting this field as set must also support queued invalidation (qi). 1ro-v 1b uncore queued invalidation support (qi) 0 = hardware does not support queued invalidations. 1 = hardware supports queued invalidations. datasheet, volume 2 325 processor configuration registers 2.21.4 gcmd_reg?global command register this register controls remapping hardware. if multiple control fields in this register need to be modified, software must serializ e the modifications through multiple writes to this register. 0ro 0buncore coherency (c) this field indicates if hardware access to the root, context, page- table and interrupt-remap structures are coherent (snooped) or not. 0 = hardware accesses to remapping structures are non- coherent. 1 = hardware accesses to remapping structures are coherent. hardware access to advanced fault log and invalidation queue are always coherent. b/d/f/type: 0/0/0/vc0premap address offset: 10?17h reset value: 0000000000f010dah access: ro-v, ro size: 64 bits bios optimal default 00000000000h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/vc0premap address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31 wo 0b uncore translation enable (te) software writes to this field to request hardware to enable/disable dma-remapping: 0 = disable dma remapping 1 = enable dma remapping hardware reports the status of the translation enable operation through the tes field in the global status register. there may be active dma requests in the platform when software updates this field. hardware mu st enable or disable remapping logic only at deterministic transaction boundaries, so that any in- flight transaction is either subj ect to remapping or not at all. hardware implementations suppor ting dma draining must drain any in-flight dma read/write requ ests queued within the root- complex before completing the translation enable command and reflecting the status of the comm and through the tes field in the global status register. the value returned on a read of this field is undefined. processor configuration registers 326 datasheet, volume 2 30 wo 0b uncore set root table pointer (srtp) software sets this field to set/update the root-entry table pointer used by hardware. the root-entry table pointer is specified through the root-entry table address (rta_reg) register. hardware reports the status of the "set root table pointer" operation through the rtps field in the global status register. the "set root table pointer" operation must be performed before enabling or re-enabling (after di sabling) dma remapping through the te field. after a "set root table pointer" operation, software must globally invalidate the context cache an d then globally invalidate of iotlb. this is required to ensure hardware uses only the remapping structures referenced by the new root table pointer, and not stale cached entries.while dma remapping hardware is active, software may update the root table pointer through this field. however, to ensure valid in-flight dma requests are deterministically rema pped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root-table pointer. clearing this bit has no effect. the value returned on read of this field is undefined. 29 ro 0b uncore set fault log (sfl) this field is valid only for impl ementations supporting advanced fault logging. software sets this field to requ est hardware to set/update the fault-log pointer used by hard ware. the fault-log pointer is specified through advanced fault log register. hardware reports the status of the 'set fault log' operation through the fls field in the global status register. the fault log pointer must be se t before enabling advanced fault logging (through eafl field). once advanced fault logging is enabled, the fault log pointer ma y be updated through this field while dma remapping is active. clearing this bit has no effect. the value returned on read of this field is undefined. 28 ro 0b uncore enable advanced fault logging (eafl) this field is valid only for impl ementations supporting advanced fault logging. software writes to this field to request hardware to enable or disable advanced fault logging: 0 = disable advanced fault logging. in this case, translation faults are reported through the fault recording registers. 1 = enable use of memory-resident fault log. when enabled, translation faults are recorded in the memory-resident log. the fault log pointer must be set in hardware (through the sfl field) before enabling advanced fault logging. hardware reports the status of the advanced fault logging enable operation through the afls field in the global status register. the value returned on read of this field is undefined. b/d/f/type: 0/0/0/vc0premap address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description datasheet, volume 2 327 processor configuration registers 27 ro 0b uncore write buffer flush (wbf) this bit is valid only for implem entations requiring write buffer flushing. software sets this field to requ est that hardware flush the root- complex internal write buffers. this is done to ensure any updates to the memory-resident remapping structures are not held in any internal write posting buffers. hardware reports the status of the write buffer flushing operation through the wbfs field in the global status register. clearing this bit has no effect. the value returned on a read of this field is undefined. 26 wo 0b uncore queued invalidation enable (qie) this field is valid only for im plementations supporting queued invalidations. software writes to this field to enable or disable queued invalidations. 0 = disable queued invalidations. 1 = enable use of queued invalidations. hardware reports the status of queued invalidation enable operation through qies field in the global status register. the value returned on a read of this field is undefined. 25 wo 0b uncore interrupt remapping enable (ire) this field is valid only for im plementations supporting interrupt remapping. 0 = disable interrupt-remapping hardware 1 = enable interrupt-remapping hardware hardware reports the status of the interrupt remapping enable operation through the ires field in the global status register. there may be active interrupt re quests in the platform when software updates this field. ha rdware must enable or disable interrupt-remapping logic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to remapping or not at all. hardware implementations must drain any in-flight interrupts requests queued in the root-c omplex before completing the interrupt-remapping enable comman d and reflecting the status of the command through the ires field in the global status register. the value returned on a read of this field is undefined. b/d/f/type: 0/0/0/vc0premap address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description processor configuration registers 328 datasheet, volume 2 24 wo 0b uncore set interrupt remap table pointer (sirtp) this field is valid only for impl ementations supporting interrupt- remapping. software sets this field to set/update the interrupt remapping table pointer used by hardware . the interrupt remapping table pointer is specified through the interrupt remapping table address (irta_reg) register. hardware reports the status of the 'set interrupt remap table pointer? operation through the ir tps field in the global status register. the 'set interrupt remap table pointer' operation must be performed before enabling or re-enabling (after disabling) interrupt-remapping hardware through the ire field. after a 'set interrupt remap table pointer' operation, software must globally invalidate the in terrupt entry cache. this is required to ensure hardware uses only the interrupt-remapping entries referenced by the new interrupt remap table pointer, and not any stale cached entries. while interrupt remapp ing is active, software may update the interrupt remapping table pointer th rough this field. however, to ensure valid in-flight interrupt requests are deterministically remapped, software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer. clearing this bit has no effect. the value returned on a read of this field is undefined. 23:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: 18?1bh reset value: 00000000h access: ro, wo size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description datasheet, volume 2 329 processor configuration registers 2.21.5 gsts_reg?global status register this register reports general remapping hardware status. b/d/f/type: 0/0/0/vc0premap address offset: 1c?1fh reset value: 00000000h access: ro, ro-v size: 32 bits bios optimal default 000000h bit access reset value rst/ pwr description 31 ro-v 0b uncore translation enable status (tes) this field indicates the status of dma-remapping hardware. 0 = dma-remapping hardware is not enabled 1 = dma-remapping hardware is enabled 30 ro-v 0b uncore root table pointer status (rtps) this field indicates the status of the root- table pointer in hardware. this field is cleared by hardware when software sets the srtp field in the global command register. this field is set by hardware when hardware completes the 'set root table pointer' operation using the value provided in the root-entry table address register. 29 ro 0b uncore fault log status (fls) this field is: ? cleared by hardware when software sets the sfl field in the global command register. ? set by hardware when hardware completes the 'set fault log pointer' operation using the va lue provided in the advanced fault log register. 28 ro 0b uncore advanced fault logging status (afls) this field is valid only for im plementations supporting advanced fault logging. it indicates the advanced fault logging status: 0 = advanced fault logging is not enabled. 1 = advanced fault logging is enabled. 27 ro 0b uncore write buffer flush status (wbfs) this field is valid only for impl ementations requiring write buffer flushing. this field indicates the status of the write buffer flush command. it is: ? set by hardware when software sets the wbf field in the global command register. ? cleared by hardware when hardware completes the write buffer flushing operation. 26 ro-v 0b uncore queued invalidation enable status (qies) this field indicates queued invalidation enable status. 0 = queued invalidation is not enabled 1 = queued invalidation is enabled 25 ro-v 0b uncore interrupt remapping enable status (ires) this field indicates the status of interrupt-remapping hardware. 0 = interrupt-remapping hardware is not enabled 1 = interrupt-remapping hardware is enabled 24 ro-v 0b uncore interrupt remapping table pointer status (irtps) this field indicates the status of the interrupt remapping table pointer in hardware. this field is: ? cleared by hardware when software sets the sirtp field in the global command register. ? set by hardware when hardware completes the set interrupt remap table pointer operation us ing the value provided in the interrupt remapping table address register. 23:0 ro 0h reserved (rsvd) processor configuration registers 330 datasheet, volume 2 2.21.6 rtaddr_reg?root-entr y table address register this register provides the base address of root-entry table. b/d/f/type: 0/0/0/vc0premap address offset: 20?27h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 0000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore root table address (rta) this register points to base of page aligned, 4 kb-sized root- entry table in system memory. hardware ignores and not implements bits 63:haw, where haw is the host address width. software specifies the base address of the root-entry table through this register, and programs it in hardware through the srtp field in the global command register. reads of this register returns value that was last programmed to it. 11:0 ro 0h reserved (rsvd) datasheet, volume 2 331 processor configuration registers 2.21.7 ccmd_reg?context command register this register manages context cache. the act of writing the uppermost byte of the ccmd_reg with the icc field set causes th e hardware to perform the context-cache invalidation. b/d/f/type: 0/0/0/vc0premap address offset: 28?2fh reset value: 0000000000000000h access: rw-v, rw, ro-v size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63 rw-v 0h uncore invalidate context-cache (icc) software requests invalidation of context-cache by setting this field. software must also set the requested invalidation granularity by programming the cirg field. software must read back and check the icc field is cl ear to confirm the invalidation is complete. software must not update this register when this field is set. hardware clears the icc field to indicate the invalidation request is complete. hardware also indica tes the granularity at which the invalidation operation was performed through the caig field. software must submit a context-cache invalidation request through this field only when there are no invalidation requests pending at this remapping hardware unit. since information from the context-cache may be used by hardware to tag iotlb entries, software must perform domain- selective (or global) invalidation of iotlb after the context cache invalidation has completed. hardware implementations reporting write-buffer flushing requirement (rwbf=1 in capability register) must implicitly perform a write buffer flush before invalidating the context cache. 62:61 rw 0h uncore context invalidation request granularity (cirg) software provides the requested invalidation gran ularity through this field when setting the icc field: 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalidation request. the target domain- id must be specified in the did field. 11 = device-selective invalidation request. the target source- id(s) must be specified through the sid and fm fields, and the domain-id (that was programmed in the context-entry for these device(s)) must be provided in the did field. hardware implementations may pr ocess an invalidation request by performing invalidation at a coarser granularity than requested. hardware indicates completion of the invalidation request by clearing the icc field. at this time, hardware also indicates the granularity at wh ich the actual invalidation was performed through the caig field. processor configuration registers 332 datasheet, volume 2 60:59 ro-v 0h uncore context actual invalidation granularity (caig) hardware reports the granularity at which an invalidation request was processed through the caig field at the time of reporting invalidation completion (by clearing the icc field). the following are the encodings for this field: 00 = reserved. 01 = global invalidation performed. this could be in response to a global, domain-selective or device-selective invalidation request. 10 = domain-selective invalidati on performed using the domain- id specified by software in the did field. this could be in response to a domain-selective or device-selective invalidation request. 11 = device-selective invalidation performed using the source-id and domain-id specified by software in the sid and fm fields. this can only be in response to a device-selective invalidation request. 58:34 ro 0h reserved (rsvd) 33:32 rw 0h uncore function mask (fm) software may use the function mask to perform device-selective invalidations on behalf of devices supporting pci express phantom functions. this field specifies which bits of the function number portion (least significant three bits) of the sid field to mask when performing device-selective invalidations. the following encodings are defined for this field: 00 = no bits in the sid field masked. 01 = mask most significant bit of function number in the sid field. 10 = mask two most significant bit of function number in the sid field. 11 = mask all three bits of function number in the sid field. the context-entries corresponding to all the source-ids specified through the fm and sid fields must have to the domain-id specified in the did field. 31:16 rw 0000h uncore source id (sid) this field indicates the source-id of the device whose corresponding context-entry needs to be selectively invalidated. this field along with the fm field must be programmed by software for device-selective invalidation requests. 15:8 ro 0h reserved (rsvd) 7:0 rw 00h uncore domain-id (did) this field indicates the id of the domain whose context-entries need to be selectively invalidated. this field must be programmed by software for both domain-selective and device- selective invalid ation requests. the capability register reports th e domain-id width supported by hardware. software must ensure that the value written to this field is within this limit. hard ware may ignore and not implement bits15:n, where n is the supported domain-id width reported in the capability register. b/d/f/type: 0/0/0/vc0premap address offset: 28?2fh reset value: 0000000000000000h access: rw-v, rw, ro-v size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description datasheet, volume 2 333 processor configuration registers 2.21.8 fsts_reg?fault status register this register indicates the various error status. b/d/f/type: 0/0/0/vc0premap address offset: 34?37h reset value: 00000000h access: rw1cs, ros-v, ro size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:16 ro 0h reserved (rsvd) 15:8 ros-v 00h powergood fault record index (fri) this field is valid only when the ppf field is set. the fri field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the ppf field was set by hardware. the value read from this field is undefined when the ppf field is clear. 7ro 0h reserved (rsvd) 6ro 0b uncore invalidation time-out error (ite) hardware detected a device-i otlb invalidation completion time-out. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not supporting device device- iotlbs implement this bit as rsvdz. 5ro 0b uncore invalidation completion error (ice) hardware received an unexpected or invalid device-iotlb invalidation completion. this could be due to either an invalid itag or invalid source-id in an invalidation completion response. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as rsvdz. 4 rw1cs 0b powergood invalidation queue error (iqe) hardware detected an error associated with the invalidation queue. this could be due to either a hardware error while fetching a descriptor from the invalidation queue, or hardware detecting an erroneous or invali d descriptor in the invalidation queue. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not su pporting queued invalidations implement this bit as rsvdz. 3ro 0b uncore advanced pending fault (apf) when this field is clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supporti ng advanced fault logging implement this bit as rsvdz. processor configuration registers 334 datasheet, volume 2 2ro 0b uncore advanced fault overflow (afo) hardware sets this field to indicate advanced fault log overflow condition. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supporting advanced fault logging implement this bit as rsvdz. 1ros-v 0b powergood primary pending fault (ppf) this field indicates if there ar e one or more pending faults logged in the fault recording registers. hardware computes this field as the logical or of fault (f) fields across all the fault recording registers of this remapping hardware unit. 0 = no pending faults in any of the fault recording registers 1 = one or more fault recording registers has pending faults. the fri field is updated by hardware whenever the ppf field is set by hardware. also, depending on the programming of fault event control register, a fault event is generated when hardware sets this field. 0 rw1cs 0b powergood primary fault overflow (pfo) hardware sets this field to indi cate overflow of fault recording registers. software writing 1 clears this field. when this field is set, hardware does not record any new faults until software clears this field. b/d/f/type: 0/0/0/vc0premap address offset: 34?37h reset value: 00000000h access: rw1cs, ros-v, ro size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description datasheet, volume 2 335 processor configuration registers 2.21.9 fectl_reg?fault event control register this register specifies the fault event interrupt message control bits. b/d/f/type: 0/0/0/vc0premap address offset: 38?3bh reset value: 80000000h access: rw, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw 1b uncore interrupt mask (im ) 0 = no masking of interrupt. when an interrupt condition is detected, hardware issues an interrupt message (using the fault event data and fault event address register values). 1 = this is the value on reset. software may mask interrupt message generation by setting this field. hardware is prohibited from sending the interrupt message when this field is set. 30 ro-v 0h uncore interrupt pending (ip) hardware sets the ip field when ever it detects an interrupt condition, which is defined as: when primary fault logging is active, an interrupt condition occurs when hardware records a fault through one of the fault recording registers and sets the ppf field in fault status register. when advanced fault logging is active, an interrupt condition occurs when hardware records a fault in the first fault record (at index 0) of the current fault log and sets the apf field in the fault status register. hardware detected error associated with the invalidation queue, setting the iqe field in the fault status register. hardware detected in valid device-iotlb in validation completion, setting the ice field in the fault status register. hardware detected device-iotlb invalidation completion time- out, setting the ite field in the fault status register. if any of the status fields in the fault status register was already set at the time of setting any of these fields, it is not treated as a new interrupt condition. the ip field is kept set by hard ware while the interrupt message is held pending. th e interrupt message co uld be held pending due to interrupt mask (im field) being set or other transient hardware conditions. the ip field is cleared by hardware as soon as the interrupt message pending condition is se rviced. this could be due to either: hardware issuing the in terrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending, or due to software clearing the im field. software servicing all the pending interrupt status fields in the fault status register as follows: ? when primary fault logging is active, software clearing the fault (f) field in all the fault recording registers with faults, causing the ppf field in fault status register to be evaluated as clear. ? software clearing other status fields in the fault status register by writing back the value read from the respective fields. 29:0 ro 0h reserved (rsvd) processor configuration registers 336 datasheet, volume 2 2.21.10 fedata_reg?fault event data register this register specifies the interrupt message data. 2.21.11 feaddr_reg?fault event address register this register specifies the interrupt message address. 2.21.12 feuaddr_reg?fault ev ent upper addr ess register this register specifies the interrupt message upper address. b/d/f/type: 0/0/0/vc0premap address offset: 3c?3fh reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:16 rw 0000h uncore extended interrupt message data (eimd): this field is valid only for im plementations supporting 32-bit interrupt data fields. hardware implementations supporting only 16-bit interrupt data may treat this field as rsvdz. 15:0 rw 0000h uncore interrupt message data (imd): data value in the interrupt request. b/d/f/type: 0/0/0/vc0premap address offset: 40?43h reset value: 00000000h access: rw size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:2 rw 00000000 h uncore message address (ma) when fault events are enabled, the contents of this register specify the dword-aligned addres s (bits 31:2) for the interrupt request. 1:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: 44?47h reset value: 00000000h access: rw size: 32 bits bit access reset value rst/ pwr description 31:0 rw 00000000h uncore message upper address (mua) hardware implementations supporting extended interrupt mode are required to implement this register. hardware implementations not supporting extended interrupt mode may treat this field as rsvdz. datasheet, volume 2 337 processor configuration registers 2.21.13 aflog_reg?advan ced fault log register this register specifies the base address of the memory-resident fault-log region. this register is treated as rsvdz for implemen tations not supporting advanced translation fault logging (afl field reported as 0 in the capability register). b/d/f/type: 0/0/0/vc0premap address offset: 58?5fh reset value: 0000000000000000h access: ro size: 64 bits bios optimal default 000h bit access reset value rst/ pwr description 63:12 ro 00000000 00000h uncore fault log address (fla) this field specifies the base of 4 kb aligned fault-log region in system memory. hardware ignores and does not implement bits 63:haw, where haw is the host address width. software specifies the base address and size of the fault log region through this register, and programs it in hardware through the sfl field in the global command register. when implemented, reads of this field return the value that was last programmed to it. 11:9 ro 0h uncore fault log size (fls) this field specifies the size of the fault log region pointed by the fla field. the size of the fault log region is 2^x * 4kb, where x is the value programmed in this register. when implemented, reads of this field return the value that was last programmed to it. 8:0 ro 0h reserved (rsvd) processor configuration registers 338 datasheet, volume 2 2.21.14 pmen_reg?protected memory enable register this register enables the dma-protected memory regions setup through the plmbase, plmlimt, phmbase, phmlimit registers. the register is always treated as ro for implementations not supporting protected memory regions (plmr and phmr fields reported as clear in the capability register). protected memory regions may be used by software to securely initialize remapping structures in memory. to avoid impact to legacy bios usage of memory, software is recommended to not overlap protected memo ry regions with any reserved memory regions of the platform reported through the reserved memory region reporting (rmrr) structures. b/d/f/type: 0/0/0/vc0premap address offset: 64?67h reset value: 00000000h access: rw, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw 0h uncore enable protected memory (epm) this field controls dma accesses to the protected low-memory and protected high-memory regions. 0 = protected memory regions are disabled. 1 = protected memory regions are enabled. dma requests accessing protected memory regions are handled as follows: ? when dma remapping is not enabled, all dma requests accessing protected memory regions are blocked. ? when dma remapping is enabled: ? dma requests processed as pass-through (translation type value of 10b in context-entry) and accessing the protected memory regions are blocked. ? dma requests with translated address (at=10b) and accessing the protected memory regions are blocked. ? dma requests that are subj ect to address remapping, and accessing the protected memory regions may or may not be blocked by hardware. for such requests, software must not depend on hardware protection of the protected memory regions, and instead program the dma-remapping page-tables to not allow dma to protected memory regions. remapping hardware access to the remapping structures are not subject to protected memory region checks. dma requests blocked due to protected memory region violation are not recorded or reported as remapping faults. hardware reports the status of the protected memory enable/disable operation through the prs field in this register. hardware implementations supporting dma draining must drain any in-flight translated dma requests queued within the root- complex before indica ting the protected memory region as enabled through the prs field. 30:1 ro 0h reserved (rsvd) 0ro-v 0h uncore protected region status (prs) this field indicates the status of protected memory regions: 0 = protected memory region(s) disabled. 1 = protected memory region(s) enabled. datasheet, volume 2 339 processor configuration registers 2.21.15 plmbase_reg?protected low-memory base register this register sets up the base address of dma-protected low-memory region below 4 gb. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as clear in the capability register). the alignment of the protected low memory region base depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding the most significant zero bit position with 0 in the value read back from the register. bits n:0 of this register is decoded by hardware as all 0s. software must set up the protected low memory region below 4 gb. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/vc0premap address offset: 68?6bh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw 000h uncore protected low-memory base (plmb) this register specifies the base of protected low-memory region in system memory. 19:0 ro 0h reserved (rsvd) processor configuration registers 340 datasheet, volume 2 2.21.16 plmlimit_reg?protected low-memory limit register this register sets up the limit address of dma-protected low-memory region below 4 gb. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as clear in the capability register). the alignment of the protected low memory region limit depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected low-memory base and limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits 31:(n+1) specifies a protec ted low-memory region of size 2^(n+1) bytes. ? programming the protected low-memory limit register with a value less than the protected low-memory base register disables the protected low-memory region. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/vc0premap address offset: 6c?6fh reset value: 00000000h access: rw size: 32 bits bios optimal default 00000h bit access reset value rst/ pwr description 31:20 rw 000h uncore protected low-memory limit (plml) this register specifies the last host physical address of the dma- protected low-memory region in system memory. 19:0 ro 0h reserved (rsvd) datasheet, volume 2 341 processor configuration registers 2.21.17 phmbase_reg?protected high-memory base register this register sets up the base address of dma-protected high-memory region. this register must be set up before enabling protected memory through pmen_reg, and must not be updated when protec ted memory regions are enabled. this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as clear in the capability register). the alignment of the protected high memory region base depends on the number of reserved bits (n:0) of this register. software may determine n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of this register are decoded by hardware as all 0s. software may set up the protected high memory region either above or below 4 gb. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/vc0premap address offset: 70?77h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw 00000h uncore protected high-memory base (phmb) this register specifies the base of protected (high) memory region in system memory. hardware ignores, and does not implement, bits 63:haw, where haw is the host address width. 19:0 ro 0h reserved (rsvd) processor configuration registers 342 datasheet, volume 2 2.21.18 phmlimit_reg?protected high-memory limit register this register sets up the limit address of dma-protected high-memory region. this register must be set up before enablin g protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as clear in the capability register). the alignment of the protected high memory region limit depends on the number of reserved bits (n:0) of this register. softwa re may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected high-memory base and limit registers functions as follows. ? programming the protected low-memory base and limit registers with the same value in bits haw:(n+1) specifies a protected low-memory region of size 2^(n+1) bytes. ? programming the protected high-memory limit register with a value less than the protected high-memory base register disa bles the protected high-memory region. software must not modify this register when protected memory regions are enabled (prs field set in pmen_reg). b/d/f/type: 0/0/0/vc0premap address offset: 78?7fh reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 000000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:20 rw 00000h uncore protected high-memory limit (phml) this register specifies the last host physical address of the dma- protected high-memory region in system memory. hardware ignores and does not implement bits 63:haw, where haw is the host address width. 19:0 ro 0h reserved (rsvd) datasheet, volume 2 343 processor configuration registers 2.21.19 iqh_reg?invalidation queue head register this register indicates the invalidation queue head. this register is treated as rsvdz by implementations reporting queued invalidatio n (qi) as not supported in the extended capability register. 2.21.20 iqt_reg?invalidation queue tail register this register indicates the invalidation tail he ad. this register is treated as rsvdz by implementations reporting queued invalidatio n (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/vc0premap address offset: 80?87h reset value: 0000000000000000h access: ro-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63:19 ro 0h reserved (rsvd) 18:4 ro-v 0000h uncore queue head (qh) this field specifies the offset ( 128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware. hardware resets this field to 0 whenever the queued invalidation is disabled (qies field clear in the global status register). 3:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: 88?8fh reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63:19 ro 0h reserved (rsvd) 18:4 rw-l 0000h uncore queue tail (qt) this field specifies the offset ( 128-bit aligned) to the invalidation queue for the command that will be written next by software. 3:0 ro 0h reserved (rsvd) processor configuration registers 344 datasheet, volume 2 2.21.21 iqa_reg?invalidation queue addr ess register this register configures the base address and size of the invalidation queue. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/vc0premap address offset: 90?97h reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 000000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw-l 0000000h uncore invalidation queue base address (iqa) this field points to the base of 4 kb aligned invalidation request queue. hardware ignores and does not implement bits 63:haw, where haw is the host address width. reads of this field return the value that was last programmed to it. 11:3 ro 0h reserved (rsvd) 2:0 rw-l 0h uncore queue size (qs) this field specifies the size of the invalidation request queue. a value of x in this field indicates an invalidation request queue of (2^x) 4 kb pages. the number of entries in the invalidation queue is 2^(x + 8). datasheet, volume 2 345 processor configuration registers 2.21.22 ics_reg?invalidation completion status register this register reports completion status of invalidation wait descriptor with interrupt flag (if) set. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. 2.21.23 iectl_reg?invalidation event control register this register specifies the invalidation event interrupt control bits. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. b/d/f/type: 0/0/0/vc0premap address offset: 9c?9fh reset value: 00000000h access: rw1cs size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31:1 ro 0h reserved (rsvd) 0 rw1cs 0b powergood invalidation wait descriptor complete (iwc) this bit indicates completion of invalidation wait descriptor with interrupt flag (if) field set. hardware implementations not supporting queued invalidations implement this field as rsvdz. b/d/f/type: 0/0/0/vc0premap address offset: a0?a3h reset value: 80000000h access: rw-l, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description 31 rw-l 1b uncore interrupt mask (im) 0 = no masking of interrupt. when an invalidation event condition is detected, hardware issues an interrupt message (using the invalidat ion event data and invalidation event address register values). 1 = this is the value on reset. software may mask interrupt message generation by setting this field. hardware is prohibited from sending the interrupt message when this field is set. processor configuration registers 346 datasheet, volume 2 2.21.24 iedata_reg?invalidat ion event data register this register specifies the invalidation event interrupt message data. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. 30 ro-v 0b uncore interrupt pending (ip) hardware sets the ip field whenever it detects an interrupt condition. interrupt condition is defined as: ? an invalidation wait descriptor with interrupt flag (if) field set completed, setting the iwc field in the invalidation completion status register. ? if the iwc field in the invalidation completion status register was already set at the time of setting this field, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. the interrupt message could be held pending due to interrupt mask (im field) being set, or due to other transient hardware conditions. the ip field is cleared by hardware as soon as the interrupt messag e pending condition is serviced. this could be due to either: ? hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the im field. ? software servicing the iwc field in the invalidation completion status register. 29:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: a0?a3h reset value: 80000000h access: rw-l, ro-v size: 32 bits bios optimal default 00000000h bit access reset value rst/ pwr description b/d/f/type: 0/0/0/vc0premap address offset: a4?a7h reset value: 00000000h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:16 rw-l 0000h uncore extended interrupt message data (eimd) this field is valid only for im plementations supporting 32-bit interrupt data fields. hardware implementations supporting only 16-bit interrupt data treat this field as rsvd. 15:0 rw-l 0000h uncore interrupt message data (imd) data value in the interrupt request. datasheet, volume 2 347 processor configuration registers 2.21.25 ieaddr_reg?invalidation event address register this register specifies the invalidat ion event interrupt message address. this register is treated as rsvdz by implementations reporting queued invalidation (qi) as not supported in the extended capability register. 2.21.26 ieuaddr_reg?invalid ation event upper address register this register specifies the invalidatio n event interrupt me ssage upper address. b/d/f/type: 0/0/0/vc0premap address offset: a8?abh reset value: 00000000h access: rw-l size: 32 bits bios optimal default 0h bit access reset value rst/ pwr description 31:2 rw-l 00000000h uncore message address (ma) when fault events are enabled, the contents of this register specify the dword-aligned addres s (bits 31:2) for the interrupt request. 1:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: ac?afh reset value: 00000000h access: rw-l size: 32 bits bit access reset value rst/ pwr description 31:0 rw-l 00000000h uncore message upper address (mua) hardware implementations supporting queued invalidations and extended interrupt mode are requir ed to implement this register. hardware implementations not supporting queued invalidations or extended interrupt mode ma y treat this field as rsvdz. processor configuration registers 348 datasheet, volume 2 2.21.27 irta_reg?interrupt rema pping table a ddress register this register provides the base address of interrupt remapping table. this register is treated as rsvdz by implem entations reporting interrupt remapping (ir) as not supported in the extended capability register. b/d/f/type: 0/0/0/vc0premap address offset: b8?bfh reset value: 0000000000000000h access: rw-l size: 64 bits bios optimal default 00000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw-l 0000000h uncore interrupt remapping table address (irta) this field points to the base of 4 kb aligned interrupt remapping table. hardware ignores and does not implement bits 63:haw, where haw is the host address width. reads of this field returns value that was last programmed to it. 11:4 ro 0h reserved (rsvd) 3:0 rw-l 0h uncore size (s) this field specifies the size of the interrupt remapping table. the number of entries in the interrupt remapping table is 2^(x+1), where x is the value programmed in this field. datasheet, volume 2 349 processor configuration registers 2.21.28 iva_reg?invalidate address register this register provides the dma address whose corresponding iotlb entry needs to be invalidated through the corresponding iotlb invalidate register. this register is a write-only register. b/d/f/type: 0/0/0/vc0premap address offset: 100?107h reset value: 0000000000000000h access: rw size: 64 bits bios optimal default 00000000h bit access reset value rst/ pwr description 63:39 ro 0h reserved (rsvd) 38:12 rw 0000000h uncore address (addr) software provides the dma addr ess that needs to be page- selectively invalidated. to make a page-selective invalidation request to hardware, software must first write the appropriate fields in this register, and then issue the appropriate page- selective invalidate command thro ugh the iotlb_reg. hardware ignores bits 63: n, where n is the maximum guest address width (mgaw) supported. 11:7 ro 0h reserved (rsvd) 6rw 0huncore invalidation hint (ih) the field provides hint to hardware about preserving or flushing the non-leaf (page-directory) entries that may be cached in hardware: 0 = software may have modified both leaf and non-leaf page- table entries corresponding to mappings specified in the addr and am fields. on a page-selective invalidation request, hardware must flush both the cached leaf and non- leaf page-table entries corre sponding to the mappings specified by addr and am fields. 1 = software has not modified any non-leaf page-table entries corresponding to mappings sp ecified in the addr and am fields. on a page-selective in validation request, hardware may preserve the cached non-leaf page-table entries corresponding to mappings spec ified by addr and am fields. 5:0 rw 00h uncore address mask (am) the value in this field specifies the number of low-order bits of the addr field that must be masked for the invalidation operation. this field enables software to request invalidation of contiguous mappings for size-aligned regions. for example: mask addr bits pages value masked invalidated 0 none 1 112 2 2 13:12 4 3 14:12 8 4 15:12 16 when invalidating mappings for super-pages, software must specify the appropriate mask value. for example, when invalidating mapping for a 2 mb page, software must specify an address mask value of at least 9. hardware implementations report the maximum supported mask value through the capability register. processor configuration registers 350 datasheet, volume 2 2.21.29 iotlb_reg?iotlb invalidate register this register invalidates iotlb. the act of writing the upper byte of the iotlb_reg with ivt field set causes the hardware to perform the iotlb invalidation. b/d/f/type: 0/0/0/vc0premap address offset: 108?10fh reset value: 0000000000000000h access: rw, rw-v, ro-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description 63 rw-v 0h uncore invalidate iotlb (ivt) software requests iotlb invalidation by setting this field. software must also set the requested invalidation granularity by programming the iirg field. a hardware clears the ivt fiel d to indicate the invalidation request is complete. hardware also indicates the granularity at which the invalidation operation was performed through the iaig field. software must not submit another invalidation request through this register while the iv t field is set, nor update the associated invalidate address register. software must not submit iotl b invalidation requests when there is a context-cache invalid ation request pending at this remapping hardware unit. hardware implementations reporting write-buffer flushing requirement (rwbf=1 in capabili ty register) must implicitly perform a write buffer flushing before invalidating the iotlb. 62:62 ro 0h reserved (rsvd) 61:60 rw 0h uncore iotlb invalidation request granularity (iirg) when requesting hardware to invalidate the iotlb (by setting the ivt field), software writes the requested invalidation granularity through this field. the following are the encodings for the field. 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalidatio n request. the target domain- id must be specified in the did field. 11 = page-selective invalidation request. the target address, mask and invalidation hint must be specified in the invalidate address register, and the domain-id must be provided in the did field. hardware implementations may pr ocess an invalidation request by performing invalidation at a coarser granularity than requested. hardware indicates completion of the invalidation request by clearing the ivt field. at this time, the granularity at which actual invalidation was performed is reported through the iaig field. 59:59 ro 0h reserved (rsvd) datasheet, volume 2 351 processor configuration registers 58:57 ro-v 0h uncore iotlb actual invalidation granularity (iaig) hardware reports the granularity at which an invalidation request was processed through this fiel d when reporting invalidation completion (by clearing the ivt field). the following are the encodings for this field. 00 = reserved. this indicates hardware detected an incorrect invalidation request and ignored the request. examples of incorrect invalidation requ ests include detecting an unsupported address mask value in invalidate address register for page-selective invalidation requests. 01 = global invalidation performed. this could be in response to a global, domain-selective, or page-selective invalidation request. 10 = domain-selective invalidati on performed using the domain- id specified by software in the did field. this could be in response to a domain-selective or a page-selective invalidation request. 11 = domain-page-selective inva lidation performed using the address, mask and hint specified by software in the invalidate address register an d domain-id specified in did field. this can be in response to a page-selective invalidation request. 56:50 ro 0h reserved (rsvd) 49 rw 0b uncore drain reads (dr) this field is ignored by hardware if the drd field is reported as clear in the capability register. when the drd field is reported as set in the capability register , the following encodings are supported for this field: 1 = hardware may complete the iotlb invalidation without draining any translated dma read requests. 1 = hardware must drain dma read requests. 48 rw 0b uncore drain writes (dw) this field is ignored by hardware if the dwd field is reported as clear in the capability register. wh en the dwd field is reported as set in the capability register , the following encodings are supported for this field: 0 = hardware may complete the iotlb invalidation without draining dma write requests. 1 = hardware must drain relevant translated dma write requests. 47:40 ro 0h reserved (rsvd) 39:32 rw 00h uncore domain-id (did) this field indicates the id of the domain whose iotlb entries need to be selectively inva lidated. this field must be programmed by software for domain-selective and page-selective invalidation requests. the capability register reports th e domain-id width supported by hardware. software must ensure that the value written to this field is within this limit. hard ware ignores and not implements bits 47:(32+n), where n is the supported domain-id width reported in the capability register. 31:0 ro 0h reserved (rsvd) b/d/f/type: 0/0/0/vc0premap address offset: 108?10fh reset value: 0000000000000000h access: rw, rw-v, ro-v size: 64 bits bios optimal default 0000000000000h bit access reset value rst/ pwr description processor configuration registers 352 datasheet, volume 2 |
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